How to eliminate Gate Ringing of parallel Mosfets ?

[goldsmith]

hello dear forum,

If I want to use parallel mosfets in a half bridge to increase output current ,
( I use IR2113 for gate drive )

the mosfets blow up in few minutes after power is ON

I suspect gate ringing becouse
I read about it in some application documents

my question ;
If I use 2 seperate gate drivers for each arm of half bridge , can I eliminate this fault ?

please look at the 2 pictures for what I mean

thank you

Hi
To avoid gate oscillations in mosfets you must use an RLD network across the GS , are you familiar or perhaps i should draw it for you ?

BTW : is your dead time value proper ? your mosfets could be gone due to the lack of proper dead time !

Best Wishes
Goldsmith

 

[anotherbrick]

hello Goldsmith,

I don't know what is a RLD network
can you add a simple schematic please

thank you

 

[KlausST]

Hi,

I assume:

R = resistor
L = inducance
D = diode

I personally avoid L. Instead i try to make it as small as possible. Often bad layouts increase L, making the circuit to oscillate.
R is a damping device. It is not that critical then L.

Diode is often used for fast switching OFF. This avoids cross conduct problems.
Caused by the R there is a slow (relatively) switchig ON, what reduces ringing and cross conduction problems.

Klaus

 

[andre_luis]

I don't know what is a RLD network
can you add a simple schematic

You can search on the Web for the keyword Snubber, although I know as RCD ( resistor, capacitor, diode ).

 

[anotherbrick]

You can search on the Web for the keyword Snubber, although I know as RCD ( resistor, capacitor, diode ).

I know what is a snubber - there is actually a RCD snubber across Drain - Source in my circuit

besides there is RD in series with Gate in my circuit

only I don't know how to place a L across Gate Driver - Gate - Source network

 

[D.A.(Tony)Stewart]

You might know what a snubber is, but there are many details to learn and control in layout,
YOu must learn to minimize the stray capacitance and inductance as well as the snubber value.

www.ti.com/lit/an/slpa010/slpa010.pdf

This explains the measurement method I described earlier and the use of ferrite (R+L )
https://www.fairchildsemi.com/application-notes/AN/AN-9005.pdf

When I said use the conjugate source impedance , that would be RL added in series to conjugate gate load of RC
If you dont understand "conjugate" ask.

This report defines how to use diode in gate
**broken link removed**

 

[goldsmith]

Hi and sorry for the delayed answer

I don't know what is a RLD network
can you add a simple schematic please

thank you

As the others said R is resistor and D is diode and L is inductor
Here a good schematic comes :


Sorry but i'm a bit lazy of making some diagrams or schematics so i did it via paint ! ha ha

Best Wishes
Goldsmith