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--*********************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--------------------------------------------------------------------------------
entity dff4 is
Port ( Data_in : in std_logic_vector(3 downto 0); -- 4 input lines
Data_out : out std_logic_vector(3 downto 0); -- 4 output lines
LE : in std_logic); -- Latch is open when LE=1, else it's closed
end dff4;
------------------------------------
architecture dff4_arch of dff4 is
begin
dff4_proc: process (LE)
begin
if rising_edge(LE) then
Data_out <= Data_in;
end if;
end process dff4_proc;
end dff4_arch;
--*********************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--------------------------------------------------------------------------------
entity cntr3 is -- counts frames 0 1 2
Port ( INCREASE : in std_logic; -- increase the counter on the falling edge
Data_out : buffer std_logic_vector(1 downto 0)); -- 2 output lines
end cntr3;
------------------------------------
architecture cntr3_arch of cntr3 is
begin
cntr3_proc: process (INCREASE)
begin
if rising_edge(INCREASE) then
if Data_out = "10" then
Data_out <= "00";
else
Data_out <= Data_out + 1;
end if;
end if;
end process cntr3_proc;
end cntr3_arch;
[b]--*********************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--------------------------------------------------------------------------------
entity main_fsm is
Port ( wrq : in std_logic; -- external data must be written to RAM
wrack : out std_logic; -- write acknowledge ( clears wrq status )
we : out std_logic; -- write enable goes to RAM /we pin
oe : out std_logic; -- output enable goes to RAM /oe pin
uld : out std_logic; -- also: A16
lld : out std_logic; -- also: mux, Din, CP, cntr
clk : in std_logic; -- main system clock, c.a. 7.5MHz
RESET : in std_logic); -- active LO
end main_fsm;
-------------
architecture main_fsm_arch of main_fsm is
type STATE_TYPE is ( -- main reset state is UDRD
UDRD, -- UPPER data read cycle ( UDRD = RESET )
LDRD, -- LOWER data read cycle
IDLE, -- no RAM write requested for this cycle
RAMWR, -- RAM write cycle
WRQCLR); -- clear wrq status cycle
signal CS, NS: STATE_TYPE;
--------------------------
begin
SYNC_PROC: process (clk,RESET) -- This is the synchronous part
begin
if (RESET = '1') then
CS <= UDRD; -- asynchronous reset. this must be included for successful synthesis
elsif (falling_edge(clk)) then
CS <= NS; -- register new state at clock edge
end if;
end process;
COMB_PROC: process (CS,wrq) -- This is the combinational part (complete case statement infers comb. logic)
begin
case CS is
when UDRD =>
lld <= '0';
uld <= '0';
we <= '1';
wrack <= '0';
NS <= LDRD;
oe <= '1';
------------------
when LDRD =>
lld <= '0';
uld <= '1';
we <= '1';
wrack <= '0';
if wrq='0' then
NS <= IDLE;
else
NS <= RAMWR;
end if;
oe <= '1';
------------------
when IDLE =>
lld <= '1';
uld <= '0';
we <= '1';
wrack <= '0';
NS <= UDRD; -- return to the beginning
oe <= '0';
-------------------
when RAMWR =>
lld <= '1';
uld <= '0';
we <= '0';
wrack <= '0';
NS <= WRQCLR;
oe <= '0';
------------------
when WRQCLR =>
lld <= '0';
uld <= '0';
we <= '1';
wrack <= '1';
NS <= LDRD;
oe <= '1';
end case;
end process;
end main_fsm_arch;
--*********************************************************
library IEEE;[/b]use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--------------------------------------------------------------------------------
entity wrequest is
Port ( wr : in std_logic; -- /wr signal from the uC
wrq : out std_logic; -- RAM write request to the FSM
wrack : in std_logic); -- reset the request
end wrequest;
------------------------------------
architecture wrequest_arch of wrequest is
begin
wrequest_proc: process (wr,wrack)
begin
if wrack = '1' then
wrq <= '0';
elsif rising_edge(wr) then
wrq <= '1';
end if;
end process wrequest_proc;
end wrequest_arch;
--*********************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--------------------------------------------------------------------------------
entity dff8hi is
Port ( Din : in std_logic_vector(7 downto 0); -- 8 input lines
Dout : out std_logic_vector(7 downto 0); -- 8 output lines
ld : in std_logic); -- load data on the rising ld edge
end dff8hi;
------------------------------------
architecture dff8hi_arch of dff8hi is
begin
dff8hi_proc: process (ld)
begin
if rising_edge(ld) then
Dout <= Din;
end if;
end process dff8hi_proc;
end dff8hi_arch;
--*********************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--------------------------------------------------------------------------------
entity hiz_buf is -- three state buffer
Port ( Din : in std_logic_vector(7 downto 0); -- 8 input lines
Dout : out std_logic_vector(7 downto 0); -- 8 output lines
oe : in std_logic); -- Latch is open when LE=1, else it's closed
end hiz_buf;
------------------------------------
architecture hiz_buf_arch of hiz_buf is
begin
hiz_buf_proc : process (oe,Din)
begin
if (oe = '1') then
Dout <= Din;
else
Dout <= "ZZZZZZZZ";
end if;
end process hiz_buf_proc;
end hiz_buf_arch;
--*********************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
----------------------------------
entity dff8z is
Port ( Data_in : in std_logic_vector(7 downto 0); -- eight bits of four pixel colours
Data_out : out std_logic_vector(7 downto 0); -- equals '1' if color LEQ frame
ld_in : in std_logic; --
oe_in : in std_logic);
end dff8z;
------------------------------------
architecture dff8z_arch of dff8z is
COMPONENT dff8hi
PORT(
Din : IN std_logic_vector(7 downto 0);
Dout : OUT std_logic_vector(7 downto 0);
ld : IN std_logic);
END COMPONENT;
-------------------
COMPONENT hiz_buf
PORT(
Din : IN std_logic_vector(7 downto 0);
Dout : OUT std_logic_vector(7 downto 0);
oe : IN std_logic);
END COMPONENT;
----------------
signal datai : std_logic_vector(7 downto 0);
----------------
begin
Inst_dff8hi: dff8hi PORT MAP(
Din => Data_in,
Dout => datai,
ld => ld_in);
------------------------------------
Inst_hiz_buf: hiz_buf PORT MAP(
Din => datai,
Dout => Data_out,
oe => oe_in);
end dff8z_arch;
--*********************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-----------------------------------
entity cmp2 is
Port ( color : in std_logic_vector(1 downto 0); -- Two bits of pixel color
pix_out : out std_logic; -- equals '1' if color > frame
frame : in std_logic_vector(1 downto 0)); -- from frame cntr
end cmp2;
------------------------------------
architecture cmp2_arch of cmp2 is
begin
cmp2_proc : process (color,frame)
begin
if (color > frame) then
pix_out <= '1';
else
pix_out <= '0';
end if;
end process cmp2_proc;
end cmp2_arch;
--*********************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
----------------------------------
entity cmp2x4 is
Port ( Data_in : in std_logic_vector(7 downto 0); -- eight bits of four pixel colours
pixels : out std_logic_vector(3 downto 0); -- equals '1' if color LEQ frame
frame : in std_logic_vector(1 downto 0)); -- from frame cntr
end cmp2x4;
------------------------------------
architecture cmp2x4_arch of cmp2x4 is
COMPONENT cmp2
PORT(
color : IN std_logic_vector(1 downto 0);
frame : IN std_logic_vector(1 downto 0);
pix_out : OUT std_logic);
END COMPONENT;
----------------
begin
Inst0_cmp2: cmp2 PORT MAP(
color => Data_in(1 downto 0),
pix_out => pixels(0),
frame => frame );
-----------------
Inst1_cmp2: cmp2 PORT MAP(
color => Data_in(3 downto 2),
pix_out => pixels(1),
frame => frame );
-----------------
Inst2_cmp2: cmp2 PORT MAP(
color => Data_in(5 downto 4),
pix_out => pixels(2),
frame => frame );
-----------------
Inst3_cmp2: cmp2 PORT MAP(
color => Data_in(7 downto 6),
pix_out => pixels(3),
frame => frame );
end cmp2x4_arch;
--*********************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--------------------------------------------------------------------------------
entity big_lcd2 is
Port ( clock_in : in std_logic; -- main clock signal : 7.5MHz.
reset_in : in std_logic; -- active high Reset signal
wr_in : in std_logic; -- rising edge means that the data from uC has just been written
-- into the external 74xx574 latch.
-- wr directly controls the /LE input of the 74xx574 latch.
lld_out : out std_logic; -- output the CP signal to the LCD pannel
uld_out : out std_logic; -- output the uld signal to the cpld2 uld_in pin.
we_out : out std_logic; -- controls the /WE line of the RAM chip.
oe_out : out std_logic; -- inverted lld signal
ext_data : in std_logic_vector(7 downto 0);
ram_data : inout std_logic_vector(7 downto 0);
LD_out : out std_logic_vector(3 downto 0);
UD_out : out std_logic_vector(3 downto 0);
Frame_in : in std_logic); -- every new frame is marked with a rising edge.
end big_lcd2;
-------------
architecture big_lcd2_arch of big_lcd2 is
-----------------
COMPONENT dff4
PORT(
Data_in : IN std_logic_vector(3 downto 0);
LE : IN std_logic;
Data_out : OUT std_logic_vector(3 downto 0));
END COMPONENT;
-----------------
COMPONENT cntr3
PORT(
INCREASE : IN std_logic;
Data_out : BUFFER std_logic_vector(1 downto 0));
END COMPONENT;
-----------------
COMPONENT dff8z
PORT(
Data_in : IN std_logic_vector(7 downto 0);
ld_in : IN std_logic;
oe_in : IN std_logic;
Data_out : OUT std_logic_vector(7 downto 0));
END COMPONENT;
-----------------
COMPONENT cmp2x4
PORT(
Data_in : IN std_logic_vector(7 downto 0);
frame : IN std_logic_vector(1 downto 0);
pixels : OUT std_logic_vector(3 downto 0));
END COMPONENT;
-----------------
COMPONENT main_fsm
PORT(
wrq : IN std_logic;
clk : IN std_logic;
RESET : IN std_logic;
wrack : OUT std_logic;
we : OUT std_logic;
uld : OUT std_logic;
lld : OUT std_logic;
oe : OUT std_logic);
END COMPONENT;
-----------------
COMPONENT wrequest
PORT(
wr : IN std_logic;
wrack : IN std_logic;
wrq : OUT std_logic);
END COMPONENT;
-----------------
signal wrqi : std_logic;
signal wracki : std_logic;
signal datai : std_logic_vector(3 downto 0);
signal lldi : std_logic;
signal uldi : std_logic;
signal Frm : std_logic_vector(1 downto 0);
-- signal ram_datai : std_logic_vector(7 downto 0);
-----------------
begin
-----------------
Inst_lo_dff4: dff4 PORT MAP(
Data_in => datai,
Data_out => LD_out,
LE => lldi);
-----------------
Inst_up_dff4: dff4 PORT MAP(
Data_in => datai,
Data_out => UD_out,
LE => uldi);
-----------------
Inst_cntr3: cntr3 PORT MAP(
INCREASE => Frame_in,
Data_out => frm);
-----------------
Inst_dff8z: dff8z PORT MAP(
Data_in => ext_data,
Data_out => ram_data,
ld_in => wr_in,
oe_in => lldi );
-----------------
Inst_cmp2x4: cmp2x4 PORT MAP(
Data_in => ram_data,
pixels => datai,
frame => Frm);
-----------------
Inst_main_fsm: main_fsm PORT MAP(
wrq => wrqi,
wrack => wracki,
we => we_out,
uld => uldi,
lld => lldi,
oe => oe_out,
clk => clock_in,
RESET => reset_in);
-----------------
Inst_wrequest: wrequest PORT MAP(
wr => wr_in,
wrq => wrqi,
wrack => wracki);
-----------------
lld_out <= lldi;
uld_out <= uldi;
end big_lcd2_arch;
--*********************************************************