how to design analog switch

[eezou]

How can I simulate the resistance of analog CMOS switch? What size of PMOS and NMOS is best for linearity?

 

[skal81]

Here the method I use:
- Put the switch ON (NMOS gate =VDD, PMOS gate=0)
- Place 2 voltage sources at each end of the switch, one with value V, the other with V+0.1~V+0.3
___
__V__| |__V+0.1__
- Do a sweep on V
- Plot the current, and you get the resistance by 0.1~0.3/I.

Remark: 0.1~0.3 it will be the voltage drop at your switch. The lower the best.

PMOS and NMOS L = minimum
W -> Start with 5u for this plot. Then depending on the resistance your system required and the operating voltage increase the P or NMOS.

Good luck

 

[sunking]

you can caculate it by hand if you know the voltage!
the PMOS and NMOS is normal 3:1(2.5:1)

 

[skal81]

I agree with sunking that you can do hand calculation. However for submicron process the result is quite diffenrent than the simulation. I once tried with 0.13u switch and the simulation value was more than twice the calculated. Hand calculation for submicron should be done with care.

 

[flushrat]

linearity is affected by device size, charge injection and clock feedthrough.
Here is a course note(p.e.allen cmos analog circuit II) on analog switch.