How to design an on-chip time Delay circuit ?

[marlboro_x]

As the title says.Could anyone guide me to some material?
Thx very much.

sincerely...
marlboro_x

Added after 1 hours 8 minutes:

When the signal is high,output should be high after about 150mS.
I used a PMOS current source to charge the Capacitor,followed by several inverters. The Cap is MOS Cap,it's too big and take large area.how to design a delay circuit using smaller Cap?

Thx a lot.

 

[pixel]

if you can do it with digital circuits.

 

[digitalheart]

I think you can do like this:
Use LM555 IC to create a Pulse wave which has duty cycle and frequency belong to your adjustment. Use this Pusle to charge a capacitor through a resistor.
Use a comparator to verify the voltage threshold on a pole of capacitor and turnup your circuit's stage. Delay time can change by change the duty cycle and frequency of the pulse. Duty cycle is more width and frequency is lower, delay time is shorter!

Added after 1 minutes:

(Sorry, frequency is higher...)

 

[Teddy]

You can modulate delay of the gate by changing current through it. Like in rinng oscillator VCOs.
In case you spend enough time with characterizing it it works.

 

[marlboro_x]

Thx digitalheart.
U showed such a good method.But it was not suitable for me.I want an on-chip delay circuit.

Teddy:
i use the way u just tell me.It was area-wasted for the big Cap.I wanna know how to modify the method or other architecture be used?

Thx all.

scincerely .
marlboro_x

 

[torrole]

Hello,

You can make a first capacitor charging generator (using cap_mos + inverter) and use a counter made with severals flip flop. When the capacitor reach the threshold value, you discharge it using inverter output, and make it charge again until the counter value is obtained.

T.