Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

How to design a+(b+c)'+c using CMOS?

Status
Not open for further replies.

seemagoyal44

Member level 1
Member level 1
Joined
Oct 20, 2007
Messages
39
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Visit site
Activity points
1,535
can anybody tell how to design a+(b+c)'+c using cmos

....2nd term b+c)' is nor gate but how to add a+c with nor that i don`t understand
 

Re: cmos layout

seemagoyal44 said:
can anybody tell how to design a+(b+c)'+c using cmos

....2nd term b+c)' is nor gate but how to add a+c with nor that i don`t understand

Still there is something wrong...First of all, Why do you call this post 'cmos layout', I really don't understand. Please be more specific.
 

Re: cmos layout

a+(b+c)'+c=((a+(b+c)'+c)')'=(a'*(b+c)*c')'
(a'*(b+c)*c')' - this is standard equation for cmos digital design. if you want I can draw circuit later...
 

Re: cmos layout

a+(b+c)'+c = a+(bbar.cbar)+c
Take + as parallel and . as series, so
4 pmos transistors are arranged as shown below

a b c (a in parallel with c and parallel with b and c which are in series)
c

( a+(b+c)'+c ) ḃar= abar.(b+c).cbar

therefore 4 NMOS transistors are arranged as

abar
b and c in parallel (abar in series with (b and c parallel) and these in series with cabr)
cbar

(use CMOS inverter for negation)
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top