I WANT TO CHECK FOR MULTIPLE CODITIONS USING IF ELSE LOOP .. for each conditions i have to call multiple modules.. how can i check my conditions and call the respective modules in verilog..
is there any goto and end syntax or similar syntaxes present in verilog
generate
if (a == 1) begin
module1_inst module1 (
.in1 (h),
.in2 (i),
.out1 (j)
);
end
else if (a == 2) begin
module2_inst module2 (
.in1 (x),
.in2 (y),
.out1 (z)
);
end
else begin
module3_inst module3 (
.in1 (h),
.in2 (i),
.out1 (j)
);
end
endgenerate
illustrated the if-else if - else condition. In this way you can use only if, only if-else branches.
i tried this but couldnt get the output. shows error in modelsim, can u kindly send me the example with 3 modules like addition, subtraction and multiplication. And call them using the if, else if and else conditions in the main module...
Can You share the error messages?
1 thing you should consider while using the generate statement is that you should not give the conditions which change dynamically.
i have tried initially with simple modules like addition, subtraction and multiplication modules but i cannot get the output,
thats why i asked for a simple example with code,