Ok, I'll try to answer some of those (as short as possible
)) )
4.) PMOS is used to drive 'high' because of the thresholdvoltage-effect
The same is true for NMOS to drive 'low'.
A NMOS device cant drive a full '1' and PMOS cant drive full '0'
Maximum Level depends on vth of the device. PMOS/NMOS aka CMOS
gives you a defined rail to rail swing
5.) The numbers you see there are usually the width and the length of the devices
(channel dimensions drawn in the layout)
If given only one number it's the width combined with a default length
6.) This is only for gates that are connected in series (NOR PMOS-Part NAND NMOS)
Rootcause is the channelresistance and the delay of the corresponding edge
7.) Static-Power is the part that is comsumed by leakage mechanisms while
the dynamicpart is caused switchingfreqency. Staticpower cant be zero
cause you cant turn of a device completely.
8.) A transmissiongate is usually used as a latch. Biggest advantage of TG's
is the small areaconsumption. It consists of one N and one PMOS, connected
in source/source drain/drain configuration. Gateconnections: NMOS CLK
PMOS inverted_CLK or the other way round.
9.) Loadcapacitance/Resistance and driverstrength (drivecurrent)
10.) Use Redrivers, reduce resistance, increase driversize change architecture
11.) Masklayers are used to produce IC's. You can have much more drawinglayers
than masklayers. Some masklayers are the results of boolean operations
applied to two or more drawinglayers. For example: you have design that
uses thick and thinoxide transistors. So you need a difference between
thin and thickoxide gates. You can achive that by drawing an extra layer
afterwards you generate your thinkoxide mask by AND'ing the Gatelayer
with the thickoxide-identification layer
12.) This depends on the tool you're using. AFAIK Path and Polys are only used
in Cadence, sorry if I'm wrong.
Polygons can have any form while Paths are more like streets.
Paths are defined by width/layer and the centerline.
13.) contact and via means basically the same. Usually VIA is used if metallayers
are connected while connections to source/drain/gate are named contacts
Stacking means that your technology allows to place vias/contacts directly
over another
14.) NMOS need to form a channel with minority charges. That only works
in a p-Substrate because electrons are minority carriers there.
The the is true for PMOS and a NWELL/n-Substrate.
Note that this is only true if you want to have normally off(depletion)
device.
15.) MOS does not need Bulks, if you take a look on SOI-Technologies
For normal technologies the bulk is used to control the backbias
of the devices and to improve latchup behaviour.
The voltagelevels of the bulks have to be choosen in such a way
that you dont forwardbias your diodes between source/drain and the bulk
16.) Designrules specify what you are allowed to draw and what not.
Metal width/spacings contact overlaps wellspacings implatoverlaps
and stuff like that. The creation of designrules is more or less black magic
You run experiments which look quite promising, afterwards you get problems
on your products and readjust
)))))
Designrules specify what the fab is able to manufacture.
If you don't follow them you're fucked.
17.) Widthrules specify how wide a specific geometry has to be
There are max and min values sometimes. Spacingrules specifiy the
distance between two shapes. Nowadays you even have spacings that
depend on the width of the drawn shapes. Makes the job a bit more
challenging
Overlaprules specify the overlap of interconnectinglayers
and their contactholes.
19.) Because you have to fix Power and critical signals first to make sure that
you have them in and that they are dimensioned properly.
Typically you get more and more signals the longer the project is running
and then you're running out of wirespace.
20.) Imagine you have a design in which you use 100 identical flipflops
You'll be faster is you draw one instance of the flipflop and copy
it 99 times.
21.) If you miss any signal check of your list your 100% fucked.
DRC is needed to make sure that your design fits to the designrules
you can easly get shorts by spacings being to small and so on ...
LVS is needed to verify that your drawn structures match the function
of your schematics. Without that you end up with a totally different function
(if it's working at all)
ERC looks for highohmic shorts in wells and in the substrate, finds
forewardbiased diodes and stuff like that.
If you're confident enough you might skip ERC and DRC in a small
metal redesign.
23.) Well, microprocessorguys need fast devices, while memoryguys
need devices with a very very low leakage current. I dont know what
the ASIC-guys do but I think they like taking the best of both worlds
26.) You can use the code for different technologies without problems.
27.) You have a lot of regular structures. Hierarchical layout is perfect for
those structures. Therefore you start with the smallest leaf and build up
hierarchy bottomup. Nevertheless TopDown design is off course used
at higher hierarchies.
28.) Total Area (Chip) divided by Cellarray Area
29.) If you design a DRAM you specify the wordlinepitch as a main-key parameter
of the array. The rowdecoder you have to draw for that array has to fit
to that wordlinepitch.
Circuits which have to meet such constrains are SenseAmps,Rowdecoder
Columndecoder and Fuses
30.) INV,TRINV,NAND,NOR,Flipflops all with different driversizes
33.) Electromigration discribes a transporteffect caused by to much current
in a wire. The wire starts to flow, getting thicker at one end and thinner
at the other. Ends up in a fail
wire. Happens only to Al/Cu Layers. Tungsten is unaffected.
37.) Clocks are usually distributed over the hole chip. Normally you would like
your clocksignal to arrive everywhere at the same time to have best
possible timing. You can achive that by many different clocktree-architectures
In the layout you should try to shield clocks and try to reduce paraitic loads
40.) You mean hammerheads ? Never drawn a hammerhead at an outputdriver
in 10 years. I think it has something to do with the cornerdevice
42.) Doing 10 years of DRAM-Layout and I have never heard of that ...
43.) Straped wordlines are a bit outdated nowadays. In the past they were
used to reduce wordline resistance
44.) Because they have to fit in the pitch (see 29)
45.) Hmm, as far as I know alignmentmarks are only placed in the kerf
The alignmentmarks in the Chip itself are mostly used for process control
46.) You want to make sure that your Voltagedrop is not to high.
Voltagedrop at VDD together with a rising VSS can cause serious trouble
in a Design. Busses are timingcritical, differential signals are also
critical so are shielded signals like biasvoltages and stuff.
Everything else is unimportant compared to the others
53.) Contactresitances are quite big.
55.) Litho-effects are worst for minimum geometries
5nm per edge is much for a 140nm wire but not for a 400nm
56.) Bias-nodes,supplyvoltages, compensation caps in analogcircuits
delay-cells
58.) Capacitive coupling in the right moment could cause a small speedup
59.) Make sure that both signals 'see' the exactly same neighbourhood
60.) 45Degrees can be used everywhere when the technology allows it.
It reduces currentdensity in the corners
61.) See 33
You usually have electromigration guidelines. Draw your layout the
fulfill those needs. You can also use Tools like Simplex to extract
Powernets and to an currentdensity-simulation
62.) Powerlines don't need slits
63.) Cause a Via cant carry as much current as the wire without Via.
If you place to much contacts you introduce a weak spot in your wiring
64.) Cause you have diffent areas on the chip. You have highly regular
structures in the Array/SenseAmp Area -> Arrayrules really tight
Then you have the logicpart -> peripheral rules quite relaxed
65.) In the production process (usually metal-layers dd-processes) big wires
might collect charges. If this charge finds a way to Gate the Gate might
break. Possible Workarounds are tiedowndiodes or the reduction
of the wirearea.
66.) Small chips, high yield, low cost, loads of work for layouters
67.) Line-End-Shortening.
Due to Lithoeffects all lineends print out significantly shorter than drawn
68.) Parasitic tyristors that you get automatically in CMOS ignite and
destroy your hardware. It's getting serious because of the shrinking
dimensions of modern technologies. Therefore the ignitionvoltage
is reduced and voila, you just killed your silicon
Can be controlled by designrules, substrate and wellcontacts, dopings
69.) see 68
70.) Metall or fuseoptions are far cheaper than Gate or ActiveArea Masks
74.) I would say whereever possible
75.) Where is the error is the most important question ?
Is there a simple workaround ? Is there enough room for the fix ?
Which layers are affected ? Is there sparelogic to use ?
87.) Accuracy, Runtime
94.) Nobodys using planar DRAM-Cells anymore because you need to much area
to get your cellcapacitance.
Stack builds up little trees from substratelevel while the Trench is digging
a hole in the substrate. I think that Trench will become dominant because
you have no planarisation problems between array and logic
Just my 2 cents
Greetings
Andi
