kennyg
Member level 2
It seems that 1.5 bits per stage Pipelined ADC architecture is very popular.
Can anyone explain it or give me some information(papers,links,whatever)
about how it works?
I can understand how the 2-bits per stage works.
Using only 2 comparators to decide 3 states(00,01,10) without losing information
confuse me.
How to compensate for the missing 11 state?
Why do we need to shift precision levels 1/4 Vref to the right from the 2 bits per stage architecture and get the residue multified by 2 instead of 4 ?
I have read some pipelined ADC papers,but they didn't explain why
1 bit-overlapping adding can get the correct digital code?
What's the mechanism behind that?
Can anyone explain it or give me some information(papers,links,whatever)
about how it works?
I can understand how the 2-bits per stage works.
Using only 2 comparators to decide 3 states(00,01,10) without losing information
confuse me.
How to compensate for the missing 11 state?
Why do we need to shift precision levels 1/4 Vref to the right from the 2 bits per stage architecture and get the residue multified by 2 instead of 4 ?
I have read some pipelined ADC papers,but they didn't explain why
1 bit-overlapping adding can get the correct digital code?
What's the mechanism behind that?