How do you get an output word other than the OSR out of a Sigma delta?

[kc295]

I can't seem to get how the output data word width (no of bits) in a sigma delta can be different than the over sampling ratio (OSR).

Example, assume we have a 64Hz baseband, so nyquist frequency is 128HZ, our modulator is capable from an SNR perspective of greater than 12 bits of resolution. Our OSR is 512X so sampling frequency is 64KHz. For simplicity sake assume a counter is our filter/decimator (aka accumulate and dump or sync filter) So we have a pcm bit stream loading into the “counter” at a 64KHz rate, we are clocking out at nyquist or 128Hz,(assume single stage decimation for simplicity) this means the counter will accumulate 512 bits per dump. The count can be anywhere from 0 to 511, and 512 bits can be decoded into a 9 bit word.

I've designed a couple of sigma delta modulators before, but my interest always ended at the pcm bit stream.
How do I get other than 9 bits out of this ADC?

I'm sure this is insanely stupid of me, but...............

 

[FvM]

You need at least second decimator to get out more than 9 bits.

 

[kc295]

Why would that make a difference? If "clock in" is 64K and clock out is Fn = 128Hz, then how can it be anything other than a 0 to 511 count for the A/D and hence 9 bits?

 

[FvM]

You can either look at 2nd order CIC decimator or other multi rate FIR filter. Their aperture window is larger than one output period. Read SD text books from Schreier.

 

[kaz1]

I can't seem to get how the output data word width (no of bits) in a sigma delta can be different than the over sampling ratio (OSR).

Example, assume we have a 64Hz baseband, so nyquist frequency is 128HZ, our modulator is capable from an SNR perspective of greater than 12 bits of resolution. Our OSR is 512X so sampling frequency is 64KHz. For simplicity sake assume a counter is our filter/decimator (aka accumulate and dump or sync filter) So we have a pcm bit stream loading into the “counter” at a 64KHz rate, we are clocking out at nyquist or 128Hz,(assume single stage decimation for simplicity) this means the counter will accumulate 512 bits per dump. The count can be anywhere from 0 to 511, and 512 bits can be decoded into a 9 bit word.

I've designed a couple of sigma delta modulators before, but my interest always ended at the pcm bit stream.
How do I get other than 9 bits out of this ADC?

I'm sure this is insanely stupid of me, but...............

When you consider an accumulator as your filter then your filter coefficients are all ones. As such your sum will be as you said 9 bits always. When your filter coefficients are different such as a regular LPF then the sum can take various values and you can choose the output bitwidth.
That doesn't mean you can have as wide ADC as you wish because the bitwidth gain has its own limitations and you don't want to waste resource.

 

[kc295]

I can't intuit anything more complicated than a counter in my head, but if I read you gentlemen correctly, in the simple system I have mentioned, I could clock in TWO 512 bits of serial data, from that construct a 10 bit output word at the nyquist rate, but then dump only the "oldest" 512 bits, clocking the newest 512 bits to the "oldest" position in the bit stream as "new" 512 bits are clocked in? And this could be extended to a larger moving average counter width up to the resolution capability of the modulator? In my example, 12 bits which would be a 4096 bit counter.

 

[FvM]

I can't intuit anything more complicated than a counter in my head

Unfortunately all higher order decimators are more than counters, they implement different weights for bits arriving at different times. Only the simple single stage CIC ("cascade integrator comb") filter alias box-car integrator corresponds to your decimator scheme where all bits have equal weight and aperture window spans the time interval between two output samples. See below aperture windows of 1 to 4 stage CIC decimators with decimation factor 10:

CIC decimators haven been frequently used in the early years of digital signal processing due to the economic multiplierless implementation, later generalized multi rate FIR filters with individually optimized response are more common.

 

[kc295]

Yes, I know that 1st order accumulate and dump filters are not used in general but they make for an easily understandable filter when one is trying to understand how you can get more bits than the OSR rate as in this trivial example.

 

[FvM]

You don't get more bits with 1- bit SD and single stage boxcar integrator.

 

[kaz1]

Yes, I know that 1st order accumulate and dump filters are not used in general but they make for an easily understandable filter when one is trying to understand how you can get more bits than the OSR rate as in this trivial example.

An efficient way to understand oversampling at ADC is to model it in Matlab/simulink. But since single bit conversion is a bit hard you can go for simpler method e.g. use 10 bit SAR ADC oversampling by 4. At best implementation you get 1 bit extra (11 bits). The details are in this link:

Increase Dynamic Range of SAR ADCs Using Oversampling | Analog Devices

Have you worked with any ADC (Δ-Σ or SAR) and run it in an oversampling mode? Did you get the expected results? Did you encounter any problems?In some previous articles general overviews of Δ-Σ and SAR (successive approximation register) ADCs, the techniques of oversampling as it relates to...

www.analog.com

The way I visualise oversampling is as follows:
If my signal is only 10 bits how do I get more info? If I just scale up the signal to 11 bits I just multiply by 2 but that scales signal and noise and just puts one zero in the lsb. With oversampling followed by decimation I get this LSB filled up with info from adjacent samples that are then discarded.

When the 10 bits SAR ADC is doing oversampling by 4 internally in the ADC chip then you are presented with 11 bits ADC device. What this also implies that if your ADC is presented as 11 bits but your application allows for further decimation then you can extend the concept and could get more dynamic range e.g. a further decimation by 2 gives 10log(2) = +3 dB (half bit). The rule here is implementation dependent. You will then add one LSB after your decimating filter implying also a gain of 6dB but only 3dB for SNR.

 

[D.A.(Tony)Stewart]

ΔDR = 10log10 (OSR) in dB for dynamic range improvement from OSR https://www.analog.com/en/technical...mic-range-of-sar-adcs-using-oversampling.html

 

[kaz1]

Hi Sunnyskyguy,
After careful analysis it turned out your link points to same one as mine above. That is ok just to make sure, two for the price of one.

 

[D.A.(Tony)Stewart]

Hi Sunnyskyguy,
After careful analysis it turned out your link points to same one as mine above. That is ok just to make sure, two for the price of one.

Yes I coincidentally found this earlier but posted the formula later after yours. This is somewhat like any averaging of random noisy frequency in a counter where the counter resolution and std. deviation improves by the sqrt (N) samples. so sqrt(4) =2 x better or 1 binary bit more of resolution, which requires more bits in memory if accumulated from a 1 bit SD converter. Over sampling by 64 makes the anti-aliasing much easier with a 2nd order filter rather than a 10th order brick wall Nyquist filter that has group delay distortion.