How do you convert a CMOS design into a different process like SOI

[sys_eng]

I have a CMOS design and like to change to a SOI process.
what's the best way to do that?

 

[kemiyun]

SOI is marketed as being almost the same as bulk processes. From layout perspective it's basically the same with minor differences and some additional rules. In the design side if you are doing analog you need to make sure everything works again from start, because transistor characteristics are quite different, and in some cases you can actually benefit from biasing the second gate. As long as you make sure everything works, SOI transistors are just CMOS but with better characteristics (arguable).

Except for these I didn't notice any difference and it was really easy to get used to SOI. But there is no streamlined migration. If you are designing analog circuits you have to simulate everything again.

 

[dick_freebird]

There's SOI and there's SOI.

Some foundries like TowerJazz have broad families that
include JI and PDSOI and the models & rules are largely
the same. CA18HA and CA18HB differ "only" in that HB
has a ~1.5um epi layer on a BOX while HA is on a heavy
doped handle (standard epi). As long as you do right by
body ties ("taps") there's no obvious difference. They
intended the SOI trench to be applied around groups of
devices (like NWell, and nmos in psub, regions) and not
per-device (and the ground rules reflect this, not at all
aggressive in active-to-trench).

They also have a more RF oriented, thinner CS18 flow
thet is closer to FDSOI. I haven't played with that.

At a previous job I worked on real FDSOI and found
many problems with device nonidealities when applied
to low power analog; the process was used only for
digital and high-current-density RF before I got there
and the models simply did not match reality in the
regions near threshold. Kink, RTN, history effects all
bit designers there and yet you couldn't get anyone to
bless the simple idea of using a body tie for anything,
even with presented the smoking gun and the evidence
of how to fix it. Downside of having an active company
founder who knows it all despite having done none of it.

If I were doing non-RF CMOS analog I'd stay away from
FDSOI, use a PDSOI that has similar structure to bulk
and then your transistors will be bulk-like (only with the
body free, which enables many neat tricks). But FDSOI
is the ticket when you have to beat the standard JI
delay*power product at a dictated working voltage.

The root question is, why do you want to change - what
are you looking for, and what are you willing to deal with
in order to get it?