How design a delay circuit for 60ns?

[asia]

hello everyone,I want to design a delay circuit, the delay time is about 6ons, how can I design it?
Thanks a lot

 

[Borber]

Try to give more details. Is signal analogue or digital? What is its frequency/repetition rate? What is its amplitude?

 

[flatulent]

One common method is to use a LC network simulating a transmission line. These are commonly called "delay lines."

 

[p_virote]

IC MAXIM have digital delay line signal .You can see at home page maxim

 

[asia]

Thanks for your answers, my design is a optical receiver, NRZ code, bit-rate is 1.25Gb/s, I think if using transmission lines ,it would be out of the IC,isn't it?

 

[Borber]

Your solution could be microstrip delay line.

 

[Btrend]

use a counter as delay element

 

[echo47]

About 12 meters of coax cable, or about 14 meters of twisted pair.

 

[asia]

the delay line should to be too long, is inverter ok?what's the delay time of an inverter?

 

[echo47]

An inverter that can handle 1.25Gb/s NRZ will have sub-nanosecond propagation delay.
If you need stable delay, you don't want to rely on gate delays.

 

[wonbef]

the delay time of an inverter mainly rely on gate delay (cgs)

 

[asia]

the other day I forget a very important thinghs, I need to delay the signal that has different amplitudes, and the smallest amplitude is only about 15mV,so the gate delay will not work,am I right?
And I do not want to use the line delay, as it is too long
I want to ask is there any good method to realize this long delay time(about 60ns,not need very accurate) using the circuit that can integrate well? Thanks a lot!

 

[nuiscet]

The delay time of an inverter is easily influenced by the power voltage, the temperture, and so on.

 

[sathi.ec]

Hi
i am attaching a doc file, i don't no how to paste image on this screen.
The circuit what i have drawn will give u the delay depending on ur design of the inverters and the two transistors.

 

[rjshmadala]

Hi asia,

presently i m also working on CDr circuits.what do u need exactly,do u mean delay the data by some time.

 

[electronrancher]

you can build a oneshot which should be pretty stable over temp, or you can draw a few slow inverters (normal nmos, pmos = 0.25/25).

the slow inverters are fine if the voltage and temp in your system are reasonably well controlled (20% voltage, 50-80C temp range). if these parameters vary a lot, you may want to use a oneshot which can be built so the charging current is proportional to mosfet threshold and independent of vcc.

for example, you can use a nmos vth - reference to make a current to charge a small cap (1-2pf, made with a large pmos gate). the threshold would be another nmos whose gate is connected to the cap. now the vth reference keeps the current independent of Vcc, and the change in vth with temp changes the current to be proportional to the change in the nmos threshold, giving pretty constant oneshot time over temp.
now you only have to worry about the cap varying over process.

 

[sunjiao3]

electronrancher, could you please make your opinion more clearly? Vth-referenced? Did you mean that you will distill the Vth? Could you please make it more clearly with some simple schematic? Thank you!
Another thing, for a delay of 60ns, I think ring oscillator composed of inverters(big size) is enough. That's what one friend said "counter". However, how to relize this delay is a problem. For example, how to distill the edge of the input signal(something related to Nyquest:? How to make sure that the delayed signal has the same shapes with the original one? As a result, RC net seems a good choice. However, how to delay the signal effectively and recover it later still deserve our pondering.
60ns delay, seems not so diffcult. So, I wonder,what about 60ms? If I need to delay a signal (not so fast, just like the signal of enable and disable) for 60ms, what is the best method? Could any one of you please give me some opinion?
:?: Thank you!

 

[wjxcom]

Hi, sathi.ec: I can't download the file. can you email to me? my email: wjx197733@126.com

 

[tuza2000]

to:electronrancher
what you mean "you can draw a few slow inverters (normal nmos, pmos = 0.25/25)",is that nmos and pmos use the same size l=0.25 w=25 or nmos w=0.25 pmos w=25?