How can I get 2M CLK signal from 19.44M Overhead signal?

[mcsdos]

what do you think about useing dcm in xilinx fpga?

 

[Davis]

Not every 2.048M clock is ok. Predator wants to get a 2.048M clock synchronous to 19.44M. That's the problem. The 63 E1s demux from STM1 are not synchronous to the STM-1 carrier either.

 

[palemoon]

if u want to get exact clk , u 'd better have a external clk sourse,
after all , ur fpga can't do it best.

 

[omid_azmoon]

maybe, you can use MT8940 or 8941