help with simple code in vhdl

[barry]

We are quibbling over semantics. You're right that 'U' is a valid state; I just wouldn't call that signal 'initialized'.

The issue here was to get poor bennzia's code working, and the code he showed did not have his signal temp 'initialized' to a specific value which would cause his simulation to fail.

 

[FvM]

It's not a matter of semantics, you simply don't understand yet the VHDL initialization rules. std_logic intializes to 'U', integer range 0 to 255 initializes to 0. So it is initialized to a meaningful value in the original code. If the code would in contrast use an unsigned signal, simulation doesn't work without explicite initialization. That's no argument for omitting initialization of integer values, it's just reporting the facts.

P.S.:

The issue here was to get poor bennzia's code working, and the code he showed did not have his signal temp 'initialized' to a specific value which would cause his simulation to fail.

You apparently missed the findings from post #9 that the original code is actually working (although it's poor in several regards).

 

[NaneBL]

Hello to everybody. This is my first post. I am glad I found this great forum.

Could you help me with this code? It is a multiplexer of four displays. I have a warning about the signal "Estado":

WARNING:Xst:1710 - FF/Latch <Estado_0> (without init value) has a constant value of 0 in block <Mux_Display>. This FF/Latch will be trimmed during the optimization process.

WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Estado_1> (without init value) has a constant value of 0 in block <Mux_Display>. This FF/Latch will be trimmed during the optimization process.

Why it says that it has a constant value of 0? I am modifying the value into the process (Estado <= Estado +1).
Do you know where is the problem?
Do you suggest me some change?

A greeting.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity Mux_Display is
	port(Clk, Reset: in std_logic;
		  In0, In1, In2, In3: in std_logic_vector(7 downto 0);
		  Anodo: out std_logic_vector(3 downto 0);
		  Display: out std_logic_vector(7 downto 0));
end Mux_Display;

architecture Behavioral of Mux_Display is
	signal Contador: unsigned(15 downto 0);
	CONSTANT Limite: INTEGER := 300000; -- To get 333 Hz
	signal Estado: unsigned(1 downto 0);
begin
	process
	begin
		wait until Clk'event and Clk='1';
		if Reset = '1' then
			Contador <= "0000000000000000"; -- Inicializamos
			Estado <= "00";
		elsif Contador > Limite then 
			Contador <= "0000000000000000"; -- Inicializamos
			Estado <= Estado + 1;
		else Contador <= Contador + 1;
		end if;
	end process;
	-- Second level Multiplexers combine 4 digits for display
	Display <= In0 WHEN Estado = "00" ELSE
              In1 WHEN Estado = "01" ELSE
              In2 WHEN Estado = "10" ELSE
              In3;
   -- Decode multiplexer driver counter for common anode display tr. Drivers
	with Estado select
		Anodo <= "1110" when "00", -- Active low outputs
					"1101" when "01",
					"1011" when "10",
					"0111" when others;
   
end Behavioral;

 

[FvM]

Your synthesis tool is clever enough to see that Contador > Limite is always false. The 16 Bit unsigned value Contadar will never reach a value of 300000.

 

[NaneBL]

Your synthesis tool is clever enough to see that Contador > Limite is always false. The 16 Bit unsigned value Contadar will never reach a value of 300000.

Sorry, I am a fool Rookie mistake. Thanks.