[SOLVED] HELP tsmc 0.35u cmos simulation

i try to simulate a low dropout voltage regulator circuit that includes a pass transistor whith w=16000u l=0.4u
when i want to simulate it, hspice shows that w is exceed wl max .
my highest wmax in library is about 200u

anybody have tsmc 0.35u model or lib that includes mosfet with wlmax= 16000u ?

I do not. However I can tell you that a straight single gate
device drawn with w=16000u is just stupid and would not
ever be done (you want a 1.6cm die in one dimension?).
So step back, assign a stripes / multiplier and a sane w
value. If you can't do it that way then parallel N sane-
geometry FET instances.

No it s not stupid work !!
please read this articles carefully then u ll see it s not crazy !
1-Full On-Chip CMOS Low-Dropout Voltage Regulator (Robert J. Milliken, Jose Silva-Martínez, Senior Member, IEEE, and Edgar Sánchez-Sinencio, Fellow, IEEE)
2-A Frequency Compensation Scheme for LDO Voltage Regulators(Chaitanya K. Chava, Member, IEEE, and José Silva-Martínez, Senior Member, IEEE)

pass mos in first has w=16000u & second one has W=6000u

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if u use multiplier coefficient Cgs & Cgd will be bigger & this destroy my results !!!
i can send u these articles if u want .

What is meant is: use (e.g) w=16, f(fingers)=1000

i think my library has problem and doesn t support nf parameter
i use number of fingers nf=80 as my max w size is 200u to simulate 16000u as below
mp 1 7 3 3 pch w=200u l=0.4u nf=80
but hspice warn job aborted!!!!
have u got 0.35u tsm.c lib ??


i simulate it as u said .but recieved this error in .lis file
mp 1 7 3 3 pmos w=200u l=0.4u m=2 nf=80

**warning** (e:\ghaznavi\new folder\my paper simule\edaboard.sp:32) parameter nf is ignored

Click to expand...

how can I solve this problem ?


thanks .

Use only multiplier option or instance pass fet as a vector.

And yes, using single strip fet with mm width is very stupid for number of reasons…

when i use multiplier coefficient for this work e.g
mp 1 7 3 3 pch w=200u l=0.4u m=80
to reach w=16000u my given result will be completely different .as u know when u multiple some transistor the capacitors will be rise in proportion m . and ro (drain/source resistance) will be reduce (1/m) . so this will affect ac analysis response .

i read the tuturial in this forum and cadense site (for finger ) but still hspice shows this error >>parameter nf is ignored
i want to know how to use number fingers in my hspice ???

anobanini said:

i think my library has problem and doesn t support nf parameter
i use number of fingers nf=80 as my max w size is 200u to simulate 16000u as below

Code:

mp 1 7 3 3 pch  w=200u l=0.4u nf=80

but hspice warn job aborted!!!!

i simulate it as u said .but recieved this error in .lis file

Code:

mp 1 7 3 3 pmos  w=200u l=0.4u m=2 nf=80

how can I solve this problem ?

Click to expand...

I fear HSPICE has a different consideration of this nomenclature as we are used to, s. below:
View attachment HSPICE__number_of_fingers.pdf

In my experience (exclusively non-HSPICE) the fingering is
handled at the mid-layer, netlisting or subcircuit, where the
w and nf / m are "massaged" to get sane overlap capacitances
and access resistances (figuring as, ad, ps, pd, etc.). If you
are working from a PDK then you might look at the chain that
takes you from schematic properties to passed arguments
to element card, and understand what "knobs" are there for
you.

Of course you could also go at it "old school" and figure the
geometry based inputs for a sane-width finger (here, I would
use electromigration reliability current density limit for the S/D
metal stripe end width, and maximum Ids per W based on your
application limits). This is one area where shrinking geometries
are definitely -not- your friend - metal w and t are reduced
while channel current density is increased. But anyway, if you
figure the attributes of one worthy finger than you can at
a minimum, instantiate (16000/wfinger) of them in your own
subcircuit representing the pass FET, plainly enough.

my problem solved

Mr Dominik Przyborowski said ::

I know this papers. Read once again posts under your thread and look on the chips micrographs. In first one, pass fet occupies rectangle of 200×240µm² while in second it seems to be rectangle with dimensions of 200×100µm². So as You sees the maximum width of single strip of pass fet in first design is no more than 100µm which results with 160 parallel connected pmosfets of 100µm/0.4µm. And of course in second design it seems to be that pass fet is not wider than 200µm and is composed from no less than 30 parallel fets.

And know imagine yourself the single strip mosfet with 16mm/0.4µm: the gate resistance of that fet (assuming 20Ω/sq of poly resistance) is equal to 800kΩ. Gate capacitance of it is around 27pF. This numbers results with cut-off frequency located in 7.4 kHz. Also, so high gate resistance results in very high input noises of fet, deterioration of gate electrical field across whole mosfet, etc.

Click to expand...

many thanks to him . his advice helped me alot .

i put multiplier coefficient (100u * 160) so my problem was on simulation method . i should cut the feed back and put source on op amp (v-feedback)pin but i made a mistake & put the source at Vin pin which dc input of regulator was there.

thank u Mr Dominik Przyborowski