Help: open loop frequency response problem for an opamp

[jordan76]

Hi

I got the following open loop frequency response plots when I set input common mode voltage level at 500mV and 100mV respectively for a rail-to-rail opamp.

It seems to me that something is wrong with 500mV case because the output phase is inverse with the input phase.

What is the reason for the differences between them?
Any clues/comments are welcome! Thanks a lot!

regards,
jordan76

 

[safwatonline]

r u sure that all transistors are ON in both cases ?

 

[surianova]

Hi

I got the following open loop frequency response plots when I set input common mode voltage level at 500mV and 100mV respectively for a rail-to-rail opamp.

It seems to me that something is wrong with 500mV case because the output phase is inverse with the input phase.

What is the reason for the differences between them?
Any clues/comments are welcome! Thanks a lot!

regards,
jordan76

For the input 500mV, the gain is more higher than 100 mV and the phase margin is negative and look like the opamp is not stable, u need to compensate it.

 

[jordan76]

r u sure that all transistors are ON in both cases ?

Yes.

I checked the DC operating point and found that for 100mV case the ouput NMOS is in linear region while it is still in saturation in case of 500mV. That may explain why the gain in 500mV case is higher than 100mV case.

Also the load capacitance is very huge(100nF). Normally it should enough for compensation purpose. Actually even if I increased the load to 1F, it is still unstable. So what is the problem???

regards,
jordan76

 

[surianova]

r u sure that all transistors are ON in both cases ?

Yes.

I checked the DC operating point and found that for 100mV case the ouput NMOS is in linear region while it is still in saturation in case of 500mV. That may explain why the gain in 500mV case is higher than 100mV case.

Also the load capacitance is very huge(100nF). Normally it should enough for compensation purpose. Actually even if I increased the load to 1F, it is still unstable. So what is the problem???

regards,
jordan76

Actually you need to find out which node is dominant pole or high impedance node in your circuit. If you put a big capacitor at the low impedance node or non-dominant, it will make the phase margin worse.

 

[safwatonline]

ok, i just wanted u to make sure that the tail curent transistor is ON as i think that 100mV is very low CM input.
if u r sure then i have no CLUE.

i keep thinking of the 100mV , this is really small value how can the diff. pair be in saturation using this value , let me give Vth=0.4 and min Veff=100mV (for the tail MOS) , then the Vcm should be at least 500mV.
i think that u may be working in sub-threshold.
also about the output MOS being in linear is that acceptable?!
anyway can u post ur schematic.
regards,
a.safwat