help on logical circuit design

[FvM]

Regarding post #16. How is the output enable of Cout and Sout controlled? If they are permanently enabled, Cin and Sin are useless because they always reflect the respective input signals. The situation would be slightly different in case of open drain outputs, but nothing of this kind has been specified.

--- Updated Jul 20, 2020 ---

My comment in post #2 is also valid for open drain signals, e.g. I2C. No suitable protocol based algorithm has been yet suggested in this thread, but there's at least an option to implement it.

Again, I don't expect that the thread is asking about open drain drivers, otherwise they would be specified from the start.

--- Updated Jul 20, 2020 ---

Available bidirectional I2C bridges like PCA9614 are using output drivers with elevated low level to recognize externally driven low state.

 

[danadakk]

Regarding post #16. How is the output enable of Cout and Sout controlled? If they are permanently enabled, Cin and Sin are useless because they always reflect the respective input signals. The situation would be slightly different in case of open drain outputs, but nothing of this kind has been specified.

The open drain aspect is configed in the pin wizard used. They are permanently enabled.

Cin and Sin complete reading the pin state in a HW fashion. One normally in code, read the pin state register, except
this is HW only design. and there was no way internally routing the pin read reg to other logic.

Again, I don't expect that the thread is asking about open drain drivers, otherwise they would be specified from the start.

He did not ask for this, but its the only way I could see doing the design, unless code was used. This is a codeless
design.


Regards, Dana.

 

[FvM]

Code is only another way to logical behavior. As far as I see, the port behavior specified in post #1 clause 1 + 2 can't be implemented with open drain ports becauses the description misses a dedicated inactive state.

 

[danadakk]

Code is only another way to logical behavior.

He clarified in follow on post he wanted HW only.

description misses a dedicated inactive state

Can you explain further why a "inactive state" is needed ? Note I am not
the brightest bulb on the planet, in fact quite under powered. So this
is a learning session for me as well.


Regards, Dana.

 

[danadakk]

michcfr, there is an issue in your definition. Say if C changes from 1 to 0, and changes S to 0,
if then we want to drive C to a 1 we cannot drive S to a 1 because it is outputting a 0. In other
words putting two drivers on a single output pin can cause a problem with one trying to drive
a 0 while the other is trying to drive a 1.

My design as shown cannot handle a single pin being driven by two sources of opposite
logic level, which is what you are asking....?

Regards, Dana.

--- Updated Jul 20, 2020 ---

I think what I will do is mod design to use a buffer with enable, disconnect its
drive once I detect I have to in order to drive pin to a 1. That will add a small
latency to transition, max a few uS.

I still would like an answer in #25 though.


Regards, Dana.