Help Needed with 16-Bit Bit Zero Detector Circuit Design

[danaoxm]

Help Needed with 16-Bit Bit Zero Detector Circuit Design

Hi everyone,

I’m working on designing a bit zero detector circuit that takes a 16-bit input and outputs two signals: one if the number of zeros is greater than 7, and another if it’s greater than 11. This circuit will be used to control charge pumps in non-volatile memory programming. I’m using Mentor Graphics tools (Pyxis, Eldo, Calibre) for this project.

Here’s my setup so far:

• Each input bit (A0 to A15) is connected to an inverter.
• The inverted bits are grouped into pairs and connected to 2-bit half adders.
• The outputs from the 2-bit adders (S0, S1, and Cout) are then connected to a 4-bit full adder to accumulate the zero count.
• Finally, the output of the 4-bit adder is connected to a 5-bit comparator to check if the zero count exceeds the thresholds of 7 and 11.

Issue: The generated waveform doesn’t match the expected output, and I’m not sure why. I’ve checked the connections and logic, but the problem persists. I suspect there may be an issue with carry propagation, timing, or the comparator configuration.

Any advice or suggestions on where I might be going wrong?

Thanks in advance for any help!

 

[BradtheRad]

outputs two signals: one if the number of zeros is greater than 7, and another if it’s greater than 11.

An obvious question arises: what output do you want if the amount comes out <=7?

 

[danaoxm]

An obvious question arises: what output do you want if the amount comes out <=7?

so there will be two comparators, one for >7 and another one for >11. it will output a high for both if the condition is met, if its <=7 or <=11, it will generate a low

 

[danaoxm]

the first one is for the 2bit adder, and the second one is for the four bit adder.

is it correct? if not, can you point out the area that maybe i wrongly connected or anything?
if its correct, what else is a possible way for me to troubleshoot, or is it because of my connection from adders to adders thats incorrect?

thank you for replying

 

[dick_freebird]

Does the evaluation have to happen real time, or is
there an interval assigned to do it after the word
has been latched from SR to holding reg?

If you have a lot of latency available, a secondary
shift reg, 4 bit counter and a couple of logic beds
(>=8 is MSB-1, >=12 is (MSB AND MSB-1 ) if you
shift-and-gate-counter-clock.

You could count the "1"s as they go by and have
the outcome within the <0> (LSB) bit interval,
using a lag or inverted clock.

 

[BradtheRad]

I suppose your setup is level-triggered? Nevertheless just in case, does everything start fresh with each calculation? Did you put in a reset of some kind where necessary?

 

[BradtheRad]

Is your method intended to prove the concept? I admit it's clever. It makes use of simpler logic gates rather than flip-flops.

As a crude way to check your work there is also a diode-resistor array.
I drew an example circuit using 4 lines although you have 16. The output volt level goes higher or lower, depending on how many input wires are low.