help needed-vhdl code

[vinodkumar]

hi frns.iam implementing an algorithm onto FPGA.to do so i need to convert real number like (0.982) etc to bit_vector or std_logic_vector.plz help me how to write code for this.or if any one had this already plz provide.
bye

 

[salma ali bakr]

see this link
hope it helps u
http://www.eda.org/fphdl/

 

[xstal]

You can go through floating point arithmatic. That will help you. Search for IEEE 754 standard. This is IEEE standard for floating point arithmatic. I have implemented floating point processor using the same standard.

 

[vinodkumar]

hi fnd.thanks for providing tht link.i have downloaded the packages frm thr.iam able to get proper simulation.but when doing synthesis iam getting problems for division.

the error which iam getting iam pasting here.

line 2549: Operator <INVALID OPERATOR> must have constant operands or first operand must be power of 2

i never expected that such errors we will get whwn we r synthesizing.

plz solve this too.
bye

 

[xstal]

Can you please post that portion of your code. It will help us pin point the problem. May be the error is due to using "FOR" loop with a variable index.

 

[rsrinivas]

check the division operator if u have one

 

[vinodkumar]

HI
thanks for responses.now i have few more problembs i need to find squareroot .i have decided to use CORDIC for this.but i need to convert the real to std_logic which is in IEEE 754 for this.so i came to my same older pb.otherwise some other way to find sqrt of real number which is synthesizable.

thanks in advance

 

[vinodkumar]

Hi friends.iam using the fixed-point format of the ieee_proposed library posted by the earlier mail.i have finished half of my project.i want need to perform the square root.i have decided to use cordic but it demands different format,plz suggest the ways to do it.

thanks in advance.
bye.
vinod.

 

[nardo520]

I NEED HELP TOO

 

[vinodkumar]

hi nardo520:
before using that package plz see that it is not synthesizing,it is only simultable.problem is there with division operator synthsis.

bye

 

[Tan]

I think the floating point values are not synthesizable yet simulatable.How is it implemented onto a FPGA.
please let me know is there any method by which i can synthesize the floating point values..

cheers

 

[nandhika]

hi

go for Fixed point implementation .........
u wont face any problem in synthesis

 

[Tan]

In case we want to implement the logarithmic values and use floating point values in vhdl and implement on the kit,then how to use floating point values.Is there any method?

 

[vinodkumar]

hi nandhika,
thanks for response.
i used earlier fixed pt. so tht i will get lesser HW.i got pb. for synthesis when iam doing for division,i hope u didn't try this.if you and didn't get sny problem,i will mail you the error which i got.
plz respond for this

bye.

 

[nandhika]

hi vinod

actually we are using fixed point representation in our projects.......

ok let me know if u have any problem i will try my level best to help u

 

[vinodkumar]

Hi nandhika
the error which i got when iam doing synthesis is the operand must be multiple of 2.otherwise xilinx ise cannot do synthesis.

bye.

 

[echo47]

Which synthesis software are you guys using? Most synthesizers do not support full integer division or floating point in HDL, because those things are very big and slow in today's FPGAs. However, those things may be included in your development tools as optimized library modules or cores. Same for logarithm and square root. Check the documentation.

 

[vinodkumar]

Hi nandhika
iam using Xilinx ise 9.1 i.now iam using ip for my algorithm implemenatation after going thru doccs.
bye