[SOLVED] help in interfacing lcd to fpga

[phobos1]

some get me right in this code for a jhd162a lcd with spartan 3e


module lcd (clk,dcout);
input clk;
output [7:0]dcout;
reg [7:0]dcout;
reg [7:0]state;
reg en;
reg mclk;
reg rs;
reg [31:0]count;
initial
begin
state = 8'h00;
mclk=1'b0;
count=31'h00000000;
end
always@(posedge clk)
begin
if (count==32'h016E3600)
mclk=~mclk;
else
count=count+1;
end
always@(posedge mclk)
begin


case (state)
0:
begin
en=1'b1;
rs=1'b1;
if (rs==1'b1)

dcout=8'h38;
en=1'b0;
state=1;

end
1:
begin
en=1'b1;
dcout=8'h0e;
en=1'b0;
state=2;

end
2:
begin
en=1'b1;
dcout=8'h01;
en=1'b0;
state=3;

end
3:
begin
en=1'b1;
dcout=8'h80;
en=1'b0;
rs=1'b0;
state=4;


end
4:
begin
en=1'b1;
if (rs==1'b0)
begin
dcout=8'h41;
en=1'b0;
state=5;
end

end
5:
begin
en=1'b1;
dcout=8'h4e;
en=1'b0;
state=6;

end
6:
begin
en=1'b1;
dcout=8'h41;
state=7;
en=1'b0;
end
7:
begin
en=1'b1;
dcout=8'h4e;
en=1'b0;
state=8;

end
8:
begin
en=1'b1;
dcout=8'h44;
en=1'b0;
state=9;

end
9:
begin
en=1'b1;
dcout=8'h48;
en=1'b0;
state=10;

end

10:
begin
en=1'b1;
dcout=8'h41;
en=1'b0;
state=11;

end
11:
begin
en=1'b1;
dcout=8'h52;
en=1'b0;
state=12;

end
12:
begin
en=1'b1;
dcout=8'h41;
en=1'b0;
state=13;

end
13:
begin
en=1'b1;
dcout=8'h4a;
en=1'b0;
state=14;

end
14:
begin
en=1'b1;
dcout=8'h41;
en=1'b0;
//state=8'h0f;
end
endcase
end
endmodule



i use a clk of 50mhz and div it to 1hz
correct me in this........

 

[soundece]

Hi..
I want instruction set and some more details about jhd162a lcd..
plz send tat details to soundrajm@gmail.com..
thanks in advnzzzzzzzzz.........
with regards..
Sounderrajan

 

[kirangowle]

Did you checked in hardware. Is it working.
I think you need to check for busy flag?