abhijeet.kumar
Newbie level 5
HEY guies help me ...please remove errore from this code...........for RFID READER
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY RFID2 IS
PORT (
SIGNAL data : IN std_logic_vector(7 DOWNTO 0);
SIGNAL address : INOUT std_logic_vector(4 DOWNTO 0);
SIGNAL we, inclock, outclock : IN std_logic;
SIGNAL q,q1 : INOUT std_logic_vector(7 DOWNTO 0);
SIGNAL compout: out std_logic);
END RFID2;
ARCHITECTURE ABHI OF RFID2 IS
TYPE mem_type IS ARRAY ( 31 DOWNTO 0) OF std_logic_vector (7 DOWNTO 0);
SIGNAL mem : mem_type;
--SIGNAL address_int : unsigned(4 DOWNTO 0);--initial address i.e. 00000
BEGIN
PROCESS (inclock,outclock, we, address)
--address_int:="00000";
VARIABLE add : unsigned(4 downto 0);--:= (others =>'0');--from address 0001
BEGIN -- PROCESS
IF (inclock = '1' AND inclock'event) THEN
--address_int <= unsigned(address);
IF we = '1' THEN
mem(To_integer(unsigned(address))) <= data;
END IF;
END IF;
--FOR i IN 0 to 31 LOOP
IF (outclock = '1' AND outclock'event) THEN
--q <= mem(to_integer(address_int));
add:="00001";
if (add < 31)then
add:= add+1;
end if;
address<= STD_LOGIC_VECTOR(add);
q<= mem (conv_integer (00000));
q1<= mem(conv_integer (address));
--end IF;
--END IF;
if (q=q1 )then
compout<='1';
else
compout<='0';
end if;
end if;
END PROCESS;
END ABHI;
Like · · Unfollow Post · 4 hours ago
Abhijeet Singh IT IS SYNTHESISE easily but cnt SIMULATE....PLEASE HELP........
The ERROR Report is.............
.ERROR:HDLCompiler:607 - "C:/Users/dell/Desktop/vhdl/RFID2/Rrfid2.vhd" Line 32: Multiple declarations of unsigned included via multiple use clauses; none are made directly visible
ERROR:HDLCompiler:607 - "C:/...
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY RFID2 IS
PORT (
SIGNAL data : IN std_logic_vector(7 DOWNTO 0);
SIGNAL address : INOUT std_logic_vector(4 DOWNTO 0);
SIGNAL we, inclock, outclock : IN std_logic;
SIGNAL q,q1 : INOUT std_logic_vector(7 DOWNTO 0);
SIGNAL compout: out std_logic);
END RFID2;
ARCHITECTURE ABHI OF RFID2 IS
TYPE mem_type IS ARRAY ( 31 DOWNTO 0) OF std_logic_vector (7 DOWNTO 0);
SIGNAL mem : mem_type;
--SIGNAL address_int : unsigned(4 DOWNTO 0);--initial address i.e. 00000
BEGIN
PROCESS (inclock,outclock, we, address)
--address_int:="00000";
VARIABLE add : unsigned(4 downto 0);--:= (others =>'0');--from address 0001
BEGIN -- PROCESS
IF (inclock = '1' AND inclock'event) THEN
--address_int <= unsigned(address);
IF we = '1' THEN
mem(To_integer(unsigned(address))) <= data;
END IF;
END IF;
--FOR i IN 0 to 31 LOOP
IF (outclock = '1' AND outclock'event) THEN
--q <= mem(to_integer(address_int));
add:="00001";
if (add < 31)then
add:= add+1;
end if;
address<= STD_LOGIC_VECTOR(add);
q<= mem (conv_integer (00000));
q1<= mem(conv_integer (address));
--end IF;
--END IF;
if (q=q1 )then
compout<='1';
else
compout<='0';
end if;
end if;
END PROCESS;
END ABHI;
Like · · Unfollow Post · 4 hours ago
Abhijeet Singh IT IS SYNTHESISE easily but cnt SIMULATE....PLEASE HELP........
The ERROR Report is.............
.ERROR:HDLCompiler:607 - "C:/Users/dell/Desktop/vhdl/RFID2/Rrfid2.vhd" Line 32: Multiple declarations of unsigned included via multiple use clauses; none are made directly visible
ERROR:HDLCompiler:607 - "C:/...