asdf44
Advanced Member level 4
It's worth noting that C code support seems to be improving.
I did a proof of concept feedback loop implementation in Vivado HLS and liked the results. The resulting code was actually higher performance than my verilog in terms of clock latency because I had placed about 4 pipeline registers in logical places (i.e. the output of the sub modules) meanwhile the HLS had optimized their placement only where/when needed.
I opted not to use HLS however because although the proof of concept was nice and compact and simple all the necessary bells and whistles such as overflow detection/correction etc would have made the C code about as long and complex as the verilog while adding another whole layer to the code-chain. The bottom line is that C isn't a ton higher level verilog.
Though there is a big plus to C considering how many algorithms have reference implementations in C and how many other programs can take C as an input. In my case I would have been able to drop my error amplifier code directly into PSIM for simulation along-side the power stage.
I did a proof of concept feedback loop implementation in Vivado HLS and liked the results. The resulting code was actually higher performance than my verilog in terms of clock latency because I had placed about 4 pipeline registers in logical places (i.e. the output of the sub modules) meanwhile the HLS had optimized their placement only where/when needed.
I opted not to use HLS however because although the proof of concept was nice and compact and simple all the necessary bells and whistles such as overflow detection/correction etc would have made the C code about as long and complex as the verilog while adding another whole layer to the code-chain. The bottom line is that C isn't a ton higher level verilog.
Though there is a big plus to C considering how many algorithms have reference implementations in C and how many other programs can take C as an input. In my case I would have been able to drop my error amplifier code directly into PSIM for simulation along-side the power stage.
