Have trouble with biasing Cree transistor

[arwen16]

We designed a bias network for Cree CG2H40010F for a triple band power amplifier on Rogers substrate (Er=2.2, h=0.787mm). We biased the transistor with the typical values of Vg=-2.6V and Vd=28V. On doing so, we observed a current of 150 mA in the gate and voltage drop in drain the moment we crossed the pinch-off voltage (-3V). We tried something new; a way to eliminate the bypass capacitors. What could be the reason our DC bias network is not working? We have used high SRF resistors and capacitors in the gate bias and stability network. All the components were working (not short circuited). We even tried changing the transistor but we had the same issue.

 

[albbg]

It seems your circuit is not stable and the transistor starts to oscillate. Possibly your idea to eliminates the need of bypass capacitor is not working. However in order to help you should attach the schematic diagram.

 

[BigBoss]

There is sequence that must be strictly followed up for biasing GaN RF transistors. Have you conformed this ??
Otherwise the transistor blows due to excess drain current.(particularly it occurs when the gate bias is applied as 0 volt with Vds is presented)

 

[FvM]

I'm with albbg. There are no bias capacitors at all. Unfortunately the line stubs intended as RF short have high impedance resonance at other frequencies.

 

[arwen16]

I'm with albbg. There are no bias capacitors at all. Unfortunately the line stubs intended as RF short have high impedance resonance at other frequencies.

I understand that but we only tested for DC. We didnt give any RF signal.

--- Updated Apr 27, 2024 ---

There is sequence that must be strictly followed up for biasing GaN RF transistors. Have you conformed this ??
Otherwise the transistor blows due to excess drain current.(particularly it occurs when the gate bias is applied as 0 volt with Vds is presented)

Yes, we did.

--- Updated Apr 27, 2024 ---

It seems your circuit is not stable and the transistor starts to oscillate. Possibly your idea to eliminates the need of bypass capacitor is not working. However in order to help you should attach the schematic diagram.

We performed the DC test first. We wanted to check if we get the right drain current. We did not give the RF signal.

 

[D.A.(Tony)Stewart]

With positive feedback at unity gain , the 1st resonance to engage when gm rises will accelerate rapidly into amplifying Vgs into saturated oscillation. To avoid this, revisit the Barkhausen Criteria, avoid ESL where this margin is lost in Vgs and establish a stable voltage source for your DC with broadband decoupling.

 

[vfone]

We tried something new; a way to eliminate the bypass capacitors.

In the proposed circuit from the datasheet of CG2H40010, I see that on the gate bias line are 5 decoupling capacitors in parallel (various values) and 6 decoupling capacitors in parallel on the drain bias line.
What do you think? What did those design engineers have in mind when they did this, with such a waste of components?

 

[arwen16]

In the proposed circuit from the datasheet of CG2H40010, I see that on the gate bias line are 5 decoupling capacitors in parallel (various values) and 6 decoupling capacitors in parallel on the drain bias line.
What do you think? What did those design engineers have in mind when they did this, with such a waste of components?

Why would you put it like that?

We have only recently started working on active circuits in our lab. We do not have the best available facilities for soldering components. We found a couple of papers in which the bias network was designed without the bypass capacitors and figured this was a good solution to our problem.

Like I said, we did the DC test first. Our logic was still that the DC test should work because caps are open at DC; hence do not contribute to the bias current.

 

[FvM]

An explanation given above says that drain current jumps suddenly due to amplifier self oscillation. If it's right, your idea of performing a pure DC test is an illusion. Besides placing bypass capacitors in bias network, resistive input and output termination will also reduce self oscillation tendency.

 

[arwen16]

An explanation given above says that drain current jumps suddenly due to amplifier self oscillation. If it's right, your idea of performing a pure DC test is an illusion. Besides placing bypass capacitors in bias network, resistive input and output termination will also reduce self oscillation tendency.

There was no jump in drain current, just the gate. I understand that we needed the bypass capacitors. Our circuit is stable. We did the EM simulation and k>1 from 30 MHz to 15 GHz.

 

[BigBoss]

There was no jump in drain current, just the gate. I understand that we needed the bypass capacitors. Our circuit is stable. We did the EM simulation and k>1 from 30 MHz to 15 GHz.

It does not mean that the amplifier doesn't oscillate. You should observe eventual oscillations up to 30 GHz with Spectrum Analyzer.

 

[D.A.(Tony)Stewart]

What values of ESL did you use in your simulator 0.8 nH/mm more or less? Any mutual coupling or crosstalk from source to gate. What was the actual impedance of the gate current sensor?
What value did you use for parasitic capacitance ?

You have to perfect your understanding at lower frequency before you can begin to understand the differences between simulations and realization at 12 GHz.

 

[FvM]

Our circuit is stable. We did the EM simulation and k>1 from 30 MHz to 15 GHz.

Seriously? How did you simulate the cable connection with unknown inductance and coupling?

There was no jump in drain current, just the gate.

Thanks for correcting. Unfortunately Ig absolute maximum rating is 4 mA, good chance to have damaged the device.

 

[volker@muehlhaus]

Our circuit is stable. We did the EM simulation and k>1 from 30 MHz to 15 GHz.

I'm sure that your "termination" at the end of the bias line in simulation was different than the wire shown in the photo.

If you have multiple samples of your PCB, you could cut one board and measure the impedance into the bias path (with wire attached at the end), then compare that to your EM result.

 

[arwen16]

I'm sure that your "termination" at the end of the bias line in simulation was different than the wire shown in the photo.

If you have multiple samples of your PCB, you could cut one board and measure the impedance into the bias path (with wire attached at the end), then compare that to your EM result.

Thank you for the suggestion. I will definitely look into this.

--- Updated Apr 28, 2024 ---

It does not mean that the amplifier doesn't oscillate. You should observe eventual oscillations up to 30 GHz with Spectrum Analyzer

We are unable to properly bias our transistor. Could you suggest how do we go about testing it for oscillations then?

 

[albbg]

I'm sure that your "termination" at the end of the bias line in simulation was different than the wire shown in the photo.

If you have multiple samples of your PCB, you could cut one board and measure the impedance into the bias path (with wire attached at the end), then compare that to your EM result.

I think is not so easy to check the impedances of the bias path especially at the higher frequencies. This is mainly due to the difficulty to accurately calibrate the launchers.

The circuit can oscillate (self-oscillation) with no RF at the input.

You said that in the simulation the circuit was stable, but you did a simulation considering also the layout (f.i.: with ADS Momentum ) ? How did you take into account the contribution of the supply wires and their mutual coupling ? You cannot place just a short in place of the power supplies.

In addition, from your picture I can see just a screw to make the pcb in contact with the PCB. Is not enough, the transistor and many part of the tracks do not share the same ground reference so you could have problems also with a correct bias network.

In any case I'm still convinced the main problem is related to the absence of bypass capacitors along the bias lines.

 

[arwen16]

I think is not so easy to check the impedances of the bias path especially at the higher frequencies. This is mainly due to the difficulty to accurately calibrate the launchers.

The circuit can oscillate (self-oscillation) with no RF at the input.

You said that in the simulation the circuit was stable, but you did a simulation considering also the layout (f.i.: with ADS Momentum ) ? How did you take into account the contribution of the supply wires and their mutual coupling ? You cannot place just a short in place of the power supplies.

In addition, from your picture I can see just a screw to make the pcb in contact with the PCB. Is not enough, the transistor and many part of the tracks do not share the same ground reference so you could have problems also with a correct bias network.

In any case I'm still convinced the main problem is related to the absence of bypass capacitors along the bias lines.

Yes, we did the EM simulation using ADS Momentum. We did not take the coupling of the DC wires into consideration. Also, the screws are used for the heat sink placed below.

 

[BigBoss]

Thank you for the suggestion. I will definitely look into this.

--- Updated Apr 28, 2024 ---

We are unable to properly bias our transistor. Could you suggest how do we go about testing it for oscillations then?

Simple...
Terminate the Input by 50 Ohm and connect SA to the Output. Even-tough the amplifier is not properly biased, you can see the oscillation if there is.
Perhaps the transistor biasing is swinging due to eventual oscillation ?? Are you sure ?