Guardring for PMOS transistors

Hello all,

I have a question about guradring arround PMOS:

should be the n+-Guardring inside of NWell or outside?

Thanks for any reply.

Inside of NWell - and this makes a good well & bulk tap, too (min. distance to the PMOS). You connect it by metal to VDD. If your PMOS source is also connected to VDD, don't let the transistor's current run through the guardRing, connect the source separately.

You can still use an additional (grounded) p+ guardring outside the nwell, if you want/need extra good isolation for/from your PMOS.

Thank you very much for your reply. Now I understand clearly about guardring for PMOS.

Hi erikl,

erikl said:

If your PMOS source is also connected to VDD, don't let the transistor's current run through the guardRing, connect the source separately .

Click to expand...

I just wanna know the reason why we shouldn't connect the source of pmos to the bulk.. What'll be the effect if we connect so.. ?
Can you please explain this in detail (or) provide me any links...

Also i've a doubt that,
What is the need of guardring ( NWell & PTAP ) & what is it doing in the chip level..

Thanks in advance..

Blue Hawk said:

I just wanna know the reason why we shouldn't connect the source of pmos to the bulk.. What'll be the effect if we connect so.. ? Can you please explain this in detail (or) provide me any links...

Click to expand...

See the explanation from this , pp. 24-25 (30-31 of the PDF).

Blue Hawk said:

What is the need of guardring ( NWell & PTAP ) & what is it doing in the chip level..

Click to expand...

Read pp. 21-27 (27-33 of the PDF) of the above lecture.