Frequency Divider Circuit issue

[pancho_hideboo]

Could anyone explain how the asynchronous reset input, M10 works in resetting the entire circuit asynchronously ?

Simply consider begavior of drain node of M10.

 

[promach]

As you can see from the following circuit screenshots, the M10 reset signal does not work in all situations.

 

[phongphanp]

May push to start and pull to close.

 

[promach]

May push to start and pull to close.

What do you mean ?

Feel free to modify https://github.com/promach/div_by_two and let us know what you modified.

 

[sherline123]

I don think it can work async. The waveform is correct corresponding to the schematic which is only can be reset when clk is falling edge.
If you want something async, why don't you put a pmos on top of M9 and change M10 connecting output and ground. This can surely pull output to '0' whenever reset come in.

 

[promach]

put a pmos on top of M9 and change M10 connecting output and ground. This can surely pull output to '0' whenever reset come in.

Hmm... this suggestion is only for asynchronous reset assertion, what about synchronous reset de-assertion ?

See this How reset synchronizers resolves reset deassertion short tutorial

 

[promach]

@sherline123

what do you mean by "put a pmos on top of M9" ?

In parallel OR In series with M9 ?

 

[sherline123]

@sherline123

what do you mean by "put a pmos on top of M9" ?

In parallel OR In series with M9 ?

Series. Just like a NOR gate. This is async.
So you want synch or async?

 

[promach]

Done.