sky_siliconthink
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That’s edaplayground, provided by DOULOS.
For Verilog/SV/UVM sim, you can run both free (Icarus) and commercial tools (questasim, vcs, xcelium) for free.
You can also do FPGA synthesis to try:
Test whether your code is synthesizable;
Try the STA commands in real tools and check the usage;
Estimate the area of your design;
Estimate timing (maximal frequency) of your design;
The commercial synthesis tool is Precision from Siemens(Mentor Graphics).
Here is a simple but instructive example:
https://www.edaplayground.com/x/u8GF
PS: to run some commercial tools, you need an E-mail of enterprise/ institution.
Many thanks to DOULOS and wish you have fun with it.
If you want to go deep with STA, you can try this link:
https://www.udemy.com/course/digita...-synthesis/?referralCode=F99007C1E5B740E11E03
For Verilog/SV/UVM sim, you can run both free (Icarus) and commercial tools (questasim, vcs, xcelium) for free.
You can also do FPGA synthesis to try:




The commercial synthesis tool is Precision from Siemens(Mentor Graphics).
Here is a simple but instructive example:

PS: to run some commercial tools, you need an E-mail of enterprise/ institution.


If you want to go deep with STA, you can try this link:
