the_penetrator
Full Member level 5
This question has no meaning as it stands!!!
FPGA is an implementation technology, a process like standard-cell is for ASIC. There are many different FPGA architectures, like fine-grain (Xilinx, Altera, others) and coarse-grain (as many research and start-ups do recently).
DSP is a kind of processor architecture. DSP means the following things:
1. MAC(s) for the usual tap operation
2. saturation arithmetic
3. zero-overhead operation for reducing looping effect
4. usually very shallow pipelines (less than 5)
5. access to multiple data memory banks (2 or 3 in most cases)
6. LUTs like for coefficient tables are nice
7. most of them don't have floating-point, you have to write
your apps for fixed-point
8. C compiler and runtime libraries support is always a issue to take
good look at
9. DMA for offloading some data mem accesses from the processor core
So, if you have a DSP in form of softcore (RTL VHDL) you can synthesize and p&r it to an FPGA of yours.
Of course, the specific FPGA resources are important, and you may have to modify your RTL (make it more implementation-specific) to better much your FPGA.
the_penetrator©
FPGA is an implementation technology, a process like standard-cell is for ASIC. There are many different FPGA architectures, like fine-grain (Xilinx, Altera, others) and coarse-grain (as many research and start-ups do recently).
DSP is a kind of processor architecture. DSP means the following things:
1. MAC(s) for the usual tap operation
2. saturation arithmetic
3. zero-overhead operation for reducing looping effect
4. usually very shallow pipelines (less than 5)
5. access to multiple data memory banks (2 or 3 in most cases)
6. LUTs like for coefficient tables are nice
7. most of them don't have floating-point, you have to write
your apps for fixed-point
8. C compiler and runtime libraries support is always a issue to take
good look at
9. DMA for offloading some data mem accesses from the processor core
So, if you have a DSP in form of softcore (RTL VHDL) you can synthesize and p&r it to an FPGA of yours.
Of course, the specific FPGA resources are important, and you may have to modify your RTL (make it more implementation-specific) to better much your FPGA.
the_penetrator©