Forcing a Logic HIGH, to a low state. How can I do this?

Forcing a Logic HIGH, to a low state. How can I do this?

I'm trying to force a Logic HIGH to a low state , when I'm troubleshooting logic circuits

How can this be done please?

For TTL and CMOS Logic chips

Hello Danny,

if your TTL-logic output is an open collector(active low output) you can use another open collector output to pull it to Low. The connection is called "Wired Or".

In CMOS it would be an open drain output. Search for NPN/PNP/PP output and you will find the differed option.

Enjoy your design work!

no, i'm trying to troubleshoot logic circuit that are in circuit, i'm trying to force a low logic level on a high logic level. i'm trying to ttroubleshoot and inject a low logic level onto a high logic state when the circuit is powered on so i can isolate which logic gate is cause the pprobleem

usually the logic outputs can be shorted for a short period of time, without being damaged. However it depends on the output type. If you know the device you can look into the datasheet to see if it has a defined specification for shorted outputs. Some driver devices have short current of 450mA and a thermal shut down -so it is designed for to tolerate a short condition. With normal logic gates it less. Only the datasheet can tell. If it is not available I would limit the current to 10mA(usuallythe max. pin current allowed on iCs) and see what the output does.

Enjoy your design work!

How can i current limit when i'm shorting the output of a gate or logic ic chip? Do I use a pull down resistor?

Yes, but any resistor forcing the logic state is overloading the driving device so there isn't a 'good' value to use. If you want to experiment, I suggest something like 47 Ohms as a starting value. Remember that somewhere, something is driving the logic level high by sourcing curent from it's supply pin, when you force it low you are diverting enough current down to ground that is can no longer sustain the high level and is therefore going to get hot quickly. There is no 'safety margin' but as pointed out, most devices will survive a short overload without permanent damage.

Also be careful with the logic operation, forcing a change of levels in a combinatorial logic circuit will give predicatable changes but in a sequential logic circuit it might have other consequences.


Brian.

Remember that somewhere, something is driving the logic level high by sourcing curent from it's supply pin, when you force it low you are diverting enough current down to ground that is can no longer sustain the high level and is therefore going to get hot quickly. There is no 'safety margin' but as pointed out, most devices will survive a short overload without permanent damage.

Click to expand...

What Can I do than , to FORCE a logic level high to a low logic level? what would you do?

ANOTHER QUESTION:
Is it ok to FORCE a logic LOW level to a Logic HIGH? the logic low from the driving is a LOW logic level ( close to zero volts ) So can I inject a HIGH logic level from an external power supply? and what do I set the current limit on the power supply to be safe to not cause damage?

What do I set the current limit for TTL and for CMOS? when trying to force a logic low to a Logic HIGH?

- - - Updated - - -

forcing a change of levels in a combinatorial logic circuit will give predicatable changes but in a sequential logic circuit it might have other consequences.

Click to expand...

What do you mean by this? what will happen?

How can you tell when a circuit is a combinatorial logic circuit VS a sequential logic circuit? from looking at the schematic ( cause I can't tell when looking at the schematic if it's a cominatorial logic circuit or a sequential logic circuit, how can you tell?

It's not safe, in my opinion, to force a level, it's more logical to put, let's say, a NOT port to change levels, also for current issues.

Think of the output of a logic gate as being a change-over switch with one pole connected to ground and the other to supply. The moving switch contact is the logic output pin. If the switch is set so the contact to ground is closed, the output is low, if the contact to supply is closed, the output is high. Suppose the contact to ground is closed, you are asking if it is safe to short it to the supply and vice versa. No matter which you try to do, you are shorting out the supply through the driving logic gate and it WILL be overloaded. You have to accept that it will be heavily overloaded, the question is: how long will it withstand the overload before being damaged. The answer is impossible to give, you would be running the gate output at many times the manufacturers rating and it will depend on the type of device as to how long it would survive. If I had to force a logic level, I would use a low value resistor as I suggested before and limit the time to 0.5 seconds at most. TTL devices tend to get very hot and just die, CMOS tends to blow a hole through it's top! Good logic design has built-in testability.

Combinatorial logic is where there is no clock or feedback loops and hence the output can always be predicted from the state of the logic inputs, sequential is where the present output depends on the previous state. If you short the logic levels in a sequential circuit it may be impossible to predict the output as the state at other parts of the circuit may not be known.

Brian.

What is a NOT port? do I have to cut the trace or lift pins on the logic IC chip?

forcing the logic state is overloading the driving device

Click to expand...

How is it overloading the driving device? explain in detail how it's overloading it please?

- - - Updated - - -

If I had to force a logic level, I would use a low value resistor as I suggested before and limit the time to 0.5 seconds at most.

Click to expand...

So you would use a low value resistor when force a logic level HIGH also and for low ? or only for the Low?

Combinatorial logic is where there is no clock or feedback loops and hence the output can always be predicted from the state of the logic inputs, sequential is where the present output depends on the previous state. If you short the logic levels in a sequential circuit it may be impossible to predict the output as the state at other parts of the circuit may not be known.

Click to expand...

So a sequential circuit is when
1.) there is clocks signals
2.) They use the ENABLE PIN on Logic chips
3.) They use the RESET pin on the logic chips
4.) what else please?

- - - Updated - - -

When using a Logic Pulsar , Is this only when you want to FORCE a low logic level to a HIGH logic level? or can I use the Logic Pulsar to FORCE a HIGH logic level to a low? either for TTL or for CMOS?

Or will the Logic Pulsar Damage or Overload the Logic IC output? for either TTL or CMOS?

The Tech that sits next to me uses an external power supply to FORCE logic levels HIGH or LOW, he has the current limit knob all the way to the MAXIMUM position. What would you set the current limit for a TTL? and for a CMOS?

Please read what I said.

ALL logic circuits have something driving them. That something is a switch (a BJT or MOSFET) behind the output pin of the device. If the switch is turned on it allows current to flow through it so other circuits can be driven. Normally, those other circuits would put a small load on the current so the device would have no problem driving them. To force the logic level to the other state, whether it is low to high or high to low, you have to provide enough curent that the device becomes incapable of sustaining the level it wants to be at.

A logic '1' is high because the device producing it is sending current through the transistor from the supply.
A logic '0' is low because the device is sinking current through the transistor to ground.

If the logic level is high and you force it low, the transistor supplying it has to pass more current and may be damaged.
If the logic level is low and you force it high, the transistor sinking it has to pass more current and may be damaged.

There is normally nothing in the output stage of a device to limit the current it will try to supply, almost all logic devices are designed to supply as much current as possible so they can drive capacitive loads at high speed.

A sequential circuit has a clock or a feedback mechanism that allows it to retain a logic state, for example a flip-flop. They do not necessarily have an enable pin or reset pin.

Brian.

what you have to do is to invest in a "pulser", this is a probe that is powered from the local board supplies and put a pulsed "1" or "0" at its tip, for a short duration (1%) of the time. This is to ensure that the excess current that results in the output circuit of the driving IC does not degrade it. So you apply this to the input of a suspect IC and use a conventional logic probe on the output with a pulse stretcher circuit in it, so you can see the LED blink. Hewlett Packard use to make them.
Frank

Why doesn't the logic pulsar overload the output? It doesn't raise the output current at all? Why is that?/

a logic probe has a pulse stretcher circuit, what does this do? An oscilloscope doesn't have a pulse strencher circuit so what iis it missing when measuring logic levels?

These same questions from Danny are on another website forum where he calls himself Billy. A few years ago he called himself Walters (remember his millions of questions?).
But he does not understand anything about electronics, does not know Ohm's Law and does not know what creates heat.

In the previous post he asked, "Why doesn't the logic pulsar overload the output" when the thread before it said, "the excess current that results". Most people understand that excess current is an overload.

All manufacturers of 74xx TTL ICs say that the absolute maximum logic low output current is 16mA but a "pulser" increases it to about 60mA by forcing it to go high.
I think that if you want an output to go high then give its inputs the logic for it to make its output go high, not force it.

Audioguru said:

I think that if you want an output to go high then give its inputs the logic for it to make its output go high, not force it.

Click to expand...

I totally agree.
My doubt was why he can't drive his logic to do that instead of forcing the output? It's a strange question btw.

How do u give the inputs the logic? To make the output switch states?

do I turn the circuit off and use an external power supply on the VCC rails and use another power supply to inject the inputs??i

Sorry, but if i don't know what is the circuit under test i can't give you more than an hint.
Can you post kind a schematic or block diagram of that logic?

There must be a documented condition of the circuit that causes the output of a logic gate to go high.
You know the truth table of the gate so you know that the inputs have that condition and you confirm it by measuring the inputs but the output of that gate does not go high.
Then either that gate is defective (probably) or the following gate's input is shorted to ground (unlikely). Forcing anything has not been used.
Which gate will you replace?

TRUE , this only works for Conbinatorial logic circuit not for Sequential circuits

Sequential circuits
1.) Have a clock Buss
2.) Have a Reset Buss
3.) Have a Enable Buss
4.) Has Feedback loops
5.) What else can you add please?

Combinatorial logic the output can always be predicted from the state of the logic inputs, sequential is where the present output depends on the previous state.

Sequential LOGIC & Troubleshooting is Different than Combinatorial Logic & Troubleshoot Circuit

Combinatorail Logic & Troubleshooting is :
1.) Check the VCC to ground on Each IC logic gate
2.) Check all the inputs and outputs and COMPARE them with the Truth tables

Sequential LOGIC & Troubleshooting is:
1.) Check the VCC to ground on Each IC logic gate
2.) Check all the inputs and outputs and COMPARE them with the Truth tables
3.) Check the clock buss
4.) Check the Enable Buss ( this is for Flip Flops , Counters ,
5.) Check the Reset buss ( this is for flip flops, counters,
6.) What else can you add please?

I don't know what the expected INPUT and OUTPUT's are suppose to be from the Connector Receptacle has 40 pins that I connect a PCB board to. There is not way I can Disconnect the inputs from the Receptacle connector , Plus I have no idea what the inputs and outputs are expected to be since i don't have a KGB Known good board.

The circuit have Flip Flops, That I have to Reset and Enable , because If I don't Reset and Enable them they will STORE the wrong Logic State even If I did change the INPUT from the Receptacle connector

How would u approach This? the Logic IC input pins have traces that go directly to the Receptacle connector without having any resistors in series , so there is no way I can disconnect the inputs unless i cut traces or Lift Pins from a dual inline package which is hard to lift pins up from right?

Several methods of forcing a logic LOW on a point in a circuit have been mentioned:

1. Short the point to ground, and take a chance on doing damage or otherwise invalidating the test.
2. Cut traces to isolate the point from any outputs and then short it to ground.
3. Lift a pin from a chip, similar to cutting a trace.

To these I would add:

4. Based on your understanding of the circuit or the function of the board, provide whatever inputs you need to the circuit to make the point in question go to logic LOW naturally. That is, convince the output that is driving the point to output a LOW instead of a HIGH. If you are troubleshooting this board you must have some idea of how it works, so perhaps you can find a way to make that output go LOW in the normal working of the board.