I'm afraid Prashanth.vinnakota sounds a bit confused on his understanding of the circuitry. But let's keep this a friendly and helpful forum.
It's true though that people often use 'latch' as a verb for what one does with a flip-flop, probably as there is no obvious verb like flip-flopped'. And 'latch' often gets swapped as a noun for flip-flop. These things often seem to happen in a world containing full of people.
However, the
original question was : how can we design a flip flop using latch ?
D-type flip-flops (DFFs) in ASICs are usually implemented at low level by two 2-to-1 muxes in series. Each mux acts as a transparent latch by having its output fed back to one of its inputs.
Each mux input select is driven from the CLK signal but uses a different CLK polarity. The first mux latches when CLK=1, the second latches when CLK=0.
This is the case in ASICs and the case in Actel PROASICPlus FPGAs, as shown in their data sheet's tile schematic. Though I cannot be certain, I'd say it's highly likely that's the basis of FPGA flip-flops, with extra circuitry to configure the flip-flop to D-type, SR, transparent etc.
Back to the ASIC case...
If it's a rising-edge clocked DFF then:
* When CLK=0, D flows through mux1 to the mux2 input
* When CLK rises, mux1 holds D and mux2 now flows D through to Q
* When CLK falls, mux2 maintains Q while mux1 flows through the next D
...and so on. This makes the CLK edge detection easy and reliable.
Hope this helps answer the original query...