FIFO depth calculation and schme architecture for CLOCK DOMAIN CROSSING

[ASIC_intl]

DXNewcastle,

Suppose for transferring data from one clock domain to another we use FIFO with FIFO full and empty indicator. Is it then we can use FIFO of any depth? Please answer generally.

 

[DXNewcastle]

Yes we can. Generally.
There will probably be data loss if the depth is inadequate.

Please refer to all previous posts.

 

[lostinxlation]

Some documents say that the grey code is used for metastability issues and not what lostinxlation is replying. Can anybody/lostinxlation explain this?

Why don't you show us "some documents" you are referring to.
Gray coding has nothing to do with metastability. its about data integrity.

And I'd have to say that you should use your brain a little bit instead of keep asking the questions on evrey reply or just reading some document and wondering.

 

[ASIC_intl]

1. Can u please provide me any document in this regard of FIFO depth calculation and clock domain crossing?

2. IN the above question you have told there may be data loss. But suppose here the sender of data has the capability to stop the data at any moment, then there will not be any data loss. Is not it?

3. How does the circuitry look like which will stop sendinh of data from master when the FIFO is full and the FIFO full indicator is on.

 

[DXNewcastle]

1. You keep asking the same questions, on this and on other threads. A useful document has been posted in repy to this question on your other thread https://www.edaboard.com/threads/204730/, which should give you the information you seek.

2. Data may be lost if the sender has the capability to stop sending for several operational and design reasons. These have already been explained in both your threads. Be aware that 'to stop sending the data at any moment' may avoid overflow of the FIFO which passes data between the clock domains, but depending on the details of your actual application which you have not supplied, then it may create the need for an earlier FIFO buffer within the first clock domain.

3. The circuit will examine the FIFO full indicator. This may be in hardware (an OR or AND gate) or in software (IF . . . . THEN . . . ). If you let us know the detail of how your application implements the buffer we can give a more detailled answer.

 

[ASIC_intl]

DXNewcastle

I went through this paper and all your explanations. Thanks for this.

I want to increase my knowledge and decision making capability on this Clock domian crossing issues.
Can you please suggest for me some more documents ? Can u please share your ideas on this more? Can u please provide me more tips? The above question is only general question toincrease my capability in this domain when I come accross solving this Clock domian crossing issues. This is not for a specific issue.

 

[DXNewcastle]

I see that I have already answered each of these questions, to the best of my ability, in previous posts, in this and in your other thread.
I'm sorry to have to tell you that if you keep asking me the same question, then I will keep replying with the same answer. Or not at all.