[SOLVED] Fan out problem in DTL circuith

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timkuc

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In above circuit I found Fan out by considering the low output of the first gate but I can not calculate fanout (dont know how to do ) as output will be HIGH and it will only be conducting reverse saturation current for diode on next gate.So how will we find the fanout when output of driving gate is high ?
 

You'd have to take a guess, find some data or do some
worst case measuring of logic diode leakage. But you could
simply say that never will it be worse than the low fanout,
and forget all about it.
 
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    timkuc

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dick_freebird said:
You'd have to take a guess, find some data or do some
worst case measuring of logic diode leakage. But you could
simply say that never will it be worse than the low fanout,
and forget all about it.
Click to expand...

Actually the constraint is that the voltage at Y should not be less then the voltage which may be considered as HIGH,becuase the reverse sturation current of next N gates will add up and give a significant current in Rc which will lead to voltage drop at Rc.If the voltage at Y goes lower than that (lowest HIGH state voltage) then the next stage result won't be proper ( because it will be working as indetermined /low state for the next gate.). The problem is reverse saturation current of diodes are very low and to get lowest HIGH state voltage at Y we need very large no. of diodes of gates at next state which does not seem practical (because reverse saturation current of diode is very low )
 

DTL was used 50 years ago so why do you talk about it today?
Have you ever looked at the extremely low reverse bias current of a diode? It is NOTHING so don't even think about how it affects fanout.
 
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    timkuc

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Thanks for replying...actually I was going with basics and I almost got the thing.But the confusion is that if we assume N gate connected to the output then the current drown from Rc will be Ni (i = current in single gate connected to output out of N) which will drop voltage at Rc ,reducing the voltage at Y.So Voltage of Y >Voh(lowest High state output of gate) to keep operation normal. So Voh should be given to calculate fanout when output is HIGH .Is my analogy is correct?
 

I do not have a datasheet for a very old DTL gate to see its reverse biased diode input current to see how many million gates will drop the output voltage to the fanout limit.
It is silly to study very old DTL gates to see a fanout of 10 when the output is low and worry about a fanout of a few million when the output is high.
 
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    timkuc

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I am happy that you replied . So I think I was correct ( I was getting millions of gate). Thank you .... I am marking it as solved:thumbsup:
 

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