Think in terms of the current loop and its voltage-drops
along the route. Your goal is to return the current as
losslessly as possible to the source (and to control how
it gets there).
ESD is generally an unpowered, handling phenomenon.
You may be tasked to tolerate certain EOS (powered
electrical pin overstress) abuse as well. But ESD design-to-
the-test is for all-but-two-pins-open, threat applied to/from
the other two, all pin combos.
A long time ago I got in the habit of using "ESD widgets"
to do full pin-pin emulation of ESD test, adding zeners and
resistors to MOSFET subcircuits so they break down
realistically. Shotgun the part, pick off any excursions which
break out from transient oxide voltage withstand (following
them down to the hit device and looking at terminal-span,
not external pin voltage) and fix anything that didn't make
it the first time.