ESD basic

[chris31]

Hi, I got some basic question on esd current discharge path.

Some of the documentation i read, when negative pulse, the current will discharge to ground. but how? didn't if D2 is forward biased, the current will go to the internal circuitry not to the ground since when forward biased current can go one path only which is upward. If from simulation, im also seeing the current go upward not to ground.

sorry, im still new with esd.

 

[betwixt]

Both diodes are normally NOT conducting. A negative voltage on the cathode of D2 will make it conduct and clamp the voltage to Vf. A high positive voltage will make D1 conduct and clamp it to Vdd. Anything between Ground and VDD will not make either diode conduct.

Brian.

 

[chris31]

Both diodes are normally NOT conducting. A negative voltage on the cathode of D2 will make it conduct and clamp the voltage to Vf. A high positive voltage will make D1 conduct and clamp it to Vdd. Anything between Ground and VDD will not make either diode conduct.

Brian.

Hi Brian, thanks for the reply. I understood your explanation, but im not quite sure with the discharge current path, where the current will be discharge to if D2 forward biased since current can only go one path in diode, my confusion is when I do some study i found out the current discharge to ground instead upward/to internal circuitry.

 

[danadakk]

This might help to show currents and voltages :

Regards, Dana.

 

[KlausST]

when negative pulse, the current will discharge to ground. but how? didn't if D2 is forward biased

Hi,

when negative!!! your red arrow is in the wrong direction.

So when the pad is negative, then D2 is forward biased. And current flows from anode to cathode.

And btw: Current flows in a loop .. not only from point A to point B.
So better draw a more complete circuit, where you can see/show the whole loop. Maybe then it´s more clear to you.

Klaus

 

[D.A.(Tony)Stewart]

The protection diodes must be very small to be faster than the CMOS yet this raises the bulk resistance that attenuates the ESD.
Initial designs in the 70'-80's looked like this to attenuate ESD.

Always use dots on junctions. Pardon my cut and paste.

 

[chris31]

I do some simulation and plot each node to see the current path.

Pardon for the messy diagram.

From pad I inject a positive current and check on the current flow. Currently, Dn diode turn on and most of current go through it. I just wondering how can it protect the internal circuitry since the current still go to the internal circuitry. Is it like create extra path for the current by go through Dn diode? is there any better analogy or theoretical explanation ?

 

[D.A.(Tony)Stewart]

You are misunderstanding the voltage divider effect of the series R and shunt diode. The 1st stage drops 15 kV to a few V and 2nd stage to 200 mV max. outside Vdd,Vss.

The duration is short enough to avoid failure but 2 stages are needed for internal CMOS gates. External ESD protection for unprotected devices may use TVS diodes with lower capacitance than power diodes.

 

[dick_freebird]

Think in terms of the current loop and its voltage-drops
along the route. Your goal is to return the current as
losslessly as possible to the source (and to control how
it gets there).

ESD is generally an unpowered, handling phenomenon.
You may be tasked to tolerate certain EOS (powered
electrical pin overstress) abuse as well. But ESD design-to-
the-test is for all-but-two-pins-open, threat applied to/from
the other two, all pin combos.

A long time ago I got in the habit of using "ESD widgets"
to do full pin-pin emulation of ESD test, adding zeners and
resistors to MOSFET subcircuits so they break down
realistically. Shotgun the part, pick off any excursions which
break out from transient oxide voltage withstand (following

them down to the hit device and looking at terminal-span,
not external pin voltage) and fix anything that didn't make
it the first time.