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Equalizing tracks on the PCBs

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mhada

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Hi,

I was trying to use the feature Relative propagation delay for matching lengths of some tracks designed on my PCB but I find that column actual and margin under relative delay turned as yellow. Why is it so? I have attached the snapshot for reference herewith. oops I do not know where to attach it????

In the match group constructed as MG1 is where I want to match the signals and I have mentioned a target. Kindly help us in this as to why the actual and margin columns are yellow.

Again whether a reference electrical set is at all required in this case.

Thanks and Regards.
 

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