Does the code indicated in the picture below actually produce the waveform attached?

[attemptingverilog]

I can’t seem to agree that the code does produce the waveform pattern in the image? From the code it seems like the register “cs” is loaded only every time start=1 (which is once in 3 clock cycles according to its assign statement code)

So cs1 would be 1 for 3 clock cycles i.e. cycles 3,4,5
cs2 would be 1 for 3 clock cycles i.e. cycles 6,7,8
cs3 would be 1 for 3 clock cycles i.e. cycles 9,10,11

Does anyone else agree or disagree?

Thank You

 

[KlausST]

Hi,

1500 kBytes of picture .... for about 0.5 kBytes of text. This is a factor of 3000.
Would you mind to reduce file sizes?

Klaus