[SOLVED] division in FPGA using verilog

Thread starter dipin
Start date Jul 30, 2014

Status: Not open for further replies.

Aug 4, 2014

dipin

Full Member level 4

HI ALL...
is it possible to do division using 2's complement form. if the number is negative,,is it possible to convert it into 2' complement and perform division. what i have done is reserve the MSB for sign bit and perform as unsigned number . so it is simple but if i need to input these valuse to any circuits then it will be a problem
thanks & regards

Status: Not open for further replies.

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[SOLVED] division in FPGA using verilog

dipin

Full Member level 4

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