Discrete Op Amp Design Help

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Hey everyone, I'm designing a discrete op amp with the following specs (per the professor):

1. Two inputs one plus , one negative

2. Capable of driving a 50 K ohm load to + 10 V

3. Frequency response DC - 10MHz + 2 db.

4. The input impedance must be at least 1 Megohm

5. The output impedance must be less than 50 ohms

8. Temperature range: 25 -- 100oC

9. The gain must be between 1000 - 1500

I found one previous post on here that didn't help me too much, apparently this isn't an uncommon project. I'm having trouble reaching the gain values, highest I can get is around 200. See attached circuit and waveform; note the differential input stage, the high gain stage (CEs), and the buffer stage (havent tweaked that yet).

What tricks do I have at my disposal for raising the gain more? It seems to distort if I try to raise resistor values. Trying to avoid PMOS components due to availability but if I must then I must..

Any help or hints are appreciated!
 

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Hi,

I'm trying to learn a bit about single supply discrete op amps, so my input may not be helpful. Isn't it better to use PNP current sources in the place of Rd1, RD2, and RGC1?

"What tricks do I have at my disposal for raising the gain more?" - I thought one method was cascading several gain stages, so their products multiply.

Can I ask why C1, C2 and C5 are so large, and not in the pF range - they aren't for compensation, are they?
 


Hey, thanks for the response!

Regarding the PNP, yes I believe so, and I have seen a few examples that utilize this, but this layout (bias resistors) is what we have been practicing in labs and so was what I utilized. If PNP offers any specific benefit I'll look into those and switch over, but I'm trying to stay NPN mainly because I have NPNs on hand.

For the gain, you're correct, I discovered the CEs weren't biased properly. I can easily achieve some nice gain, but the signals distort or cut off at the extreme edges of their amplitudes, so now I'm stuck with that problem.

The C1, C2s etc. are only to block DC voltage so the DC bias from one stage does not affect another stage; again, these are values we use in labs for this purpose and I've never really questioned it.
 
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    d123

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Hi,

Thanks, if you have time to skim read schematics, if not details, possibly "Audio Power Amplifier Design Handbook" by Douglas Self is one single example of BJT op amp design that can be quite insightful in several places.

Also, doubt it's of use, but have you looked into any benefits from choosing a different architecture, like folded cascode, etc.?

The attached pdf, while it's about low voltage design, etc., has a dual NPN input design for rail-to-rail, not sure if you can glean anything useful from that document or I've missed the issue.

- - - Updated - - -

Hi again,

Maybe slides 7 and 8 of the "ECE 255 Lecture..." about Improving Op Amp Voltage Gain and Reducing Output Resistance have something applicable to your design process/path in them.

The Analog Devices tutorial MT-035, "Op Amp Inputs, Outputs, Single-Supply, and Rail-to-Rail Issues" says the following on page 8:
"OUTPUT STAGES
The earliest IC op amp output stages were NPN emitter followers with NPN current sources or resistive pull-downs, as shown in Figure 6A. Naturally, the slew rates were greater for positive-going than they were for negative-going signals.
While all modern op amps have push-pull output stages of some sort, many are still asymmetrical, and have a greater slew rate in one direction than the other. Asymmetry tends to introduce distortion on ac signals and generally results from the use of IC processes with faster NPN than PNP transistors. It may also result in an ability of the output to approach one supply more closely than the other in terms of saturation voltage."

Again, not sure if any of this helps at all...
 

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You need to learn about how to bias a transistor. I simulated your transistor Q3 to show that it has no voltage gain because the collector DC voltage is less than its base voltage.
The collector voltage is about +5.3V but the base voltage is about +10V.

Also the load of the next transistor and its biasing resistors is about 220k which is much less than its 470k collector resistor that also reduces the gain.
Your transistors Q4 and Q5 have the same problems and the output impedance is much higher than the required 50 ohms.

I changed the base voltage to about 1V and reduced the collector and emitter resistors to get some voltage gain.
 

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I don't hear the point commented yet, you want to design an OP, but the shown circuit is an AC amplifier which can't work as OP.

Start anew with an OP topology from analog design text book, e.g. Gray/Hurst/Lewis/Meyer, Analysis and Design of Analog Integrated Circuits.
 
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    d123

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I agree than an opamp must be able to amplify DC and AC.
The wrongly biased transistor had a gain of only 1 because it was acting as a diode:
 

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If you want an easy cheat, dig up an old Silicon General,
National Semiconductor, Fairchild, et all databook and
check out the simpler op amp designs. Back when men
were men and engineers ran companies, they would
publish schematics as a point of pride (sometimes even
without embedding false bits as "gotchas" for the copy-
cats who would come later).

You will find op amps that are not much more complex
than what you've drawn, but work.
 

I have to say, datasheets are less generous these days, it's a shame as they're a very good learning tool. And from the short time I've been interested in electronics, I second your witticism/truism, you can see people were proud to share their designs/achievements, like the - I think, Widlar - 1V op amp schematic in all it's complex glory and easygoing generous description of functions and blocks, and so on. Patents, patents...
 
I dug up some documentation on biasing BJTs, and lo and behold I got the gain to finally work! And the buffer amplifier is producing the proper output impedance. You were absolutely right about improper BJT biasing, I was having a hard time finding a good explanation on where to start and what to design for when picking R values from scratch.

Now I'm wondering how to get the bandwidth to operate from DC all the way to 10 MHz.. seems like a tall order. When I set "AC" on the inverting amp source to "0" it produces a fine bandwidth, but both inputs set to 1 creates a disgusting mess.

EDIT: It's entirely possible I'm just simulating it wrong, I'm not the best with PSPICE/OrCAD.

- - - Updated - - -


I managed to find a discrete databook from national semiconductor, taking your advice haha
 

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You need to set the inputs to their true balance, in
the sense of putting the entire signal chain linear and
the output centered, if you want a proper small signal
AC analysis. Usually that's best done in a closed loop
setup, the op amp then does the work for you. If you
have a split supply symmetric about ground then set
it up in noninverting, A=100 configuration and put the
AC stimulus to INP.

For AC analysis to make sense you should only have
one stimulus at a time (unless you're looking for some
thing like intermodulation) with AC=1. Putting both
inputs AC=1 would tend to make difference voltage
be zero-ish.

You have to pick off the input difference voltage (use vcvs
so that phase and amplitude, differential, are preserved -
subtracting VM(INM) from VM(INP) loses phase relation,
but VM(vcvs_output) will include the phase relation)
and look at VM(OUT)/VM(vcvs_output) for where it
hits =1.
 

Do you know how to roughly calculate the voltage gain of a transistor?
 

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Just setting one of the AC values to 1 and the other to 0 seems to get a much better BW. Attached it along with the new time function, which shows a gain of a bit over 1k as the 10mV input is driven to ±10V as specs requested.

Not sure how to set inputs to 'true balance', I'll need to look that up.

- - - Updated - - -

Audioguru said:
Do you know how to roughly calculate the voltage gain of a transistor?
Click to expand...

Rc / Re? I tried to bias the circuit with this in mind but then started changing values to accommodate the cutoff etc.
 

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If the voltage divider sets the base voltage of a common emitter transistor too high then the collector voltage will be too low and cause the transistor to saturate and to clip the bottom of the waveform.
If the voltage divider sets the base voltage of a common emitter transistor too low then the collector voltage will be too high and cause the transistor to cutoff and to clip the top of the waveform.

An opamp is always DC-coupled (yours is not because it has AC coupling capacitors) and when the voltage at both inputs are almost the same then the output should be at half the supply voltage. Then the amplifier is balanced.
 

Should I remove the AC coupling capacitors then? I set them to 100u since higher values seemed to improve the BW at the lower frequencies (still having trouble maintaining spec at the 1MegHz level, it drops to -3dB there and even worse when tested in lab).

Another thing with the lab testing, a 10mV input measures on the oscilloscope as 20mVpp but the output waveform is 12Vpp even though it simulated at +12V and -12V. Does this mean my gain is essentially HALF of what I need it to be? Need to add a couple more CEs? Or am I just setting up the scope incorrectly?
 

An opamp does not have coupling capacitors and works from DC to a fairly high AC frequency. A coupling capacitor's reactance in series with the resistance to ground it feeds reduces the level of low frequencies at -3dB per octave (the RC vs frequency formula is simple).
If you remove the coupling capacitors then you must re-design the biasing because then each stage will amplify the DC from the previous stage.

A simulation input is the peak voltage of the waveform. Peak to peak is double the peak level.

I do not know why your sim cuts frequencies above 1MHz. In the lab if you use a solderless breadboard then its rows of contacts and many wires all over the place have capacitance between them that cut high frequencies and add interference picked up by these "antennas".
 


Ok so I'll remove the caps and rebias the circuit, in our classes we were always told to use caps between stages and I never questioned it. Even other students told me that.

For the peak to peak: Okay, so when I simulate, I observe the waveform's top peak at +10v and its bottom peak at -10v, so its Vpp should be 20. But when built and measured it is half that. That is definitely not good. Should I design for a simulated gain of double, and then build it expecting the gain to drop by half? The circuit will likely cut off the upper and lower amplitudes if I try to get the gain much higher (I think)?

I also might have to just bite the bullet and solder this circuit in order to meet spec
 

In your first post the spec's for the amplifier say a frequency response from DC so coupling capacitors must not be used.
You cannot measure gain if a stage is clipping. Turn down the input level so the output shows no clipping.
Gain is the amount of amplification, not the maximum output level. Your maximum output level and gain are restricted by the high values of the emitter resistors.
 

I don't see anything in your professor's specs (post 1)
that says you couldn't use a PNP here and there. Think
about it.
 

dick_freebird said:
I don't see anything in your professor's specs (post 1)
that says you couldn't use a PNP here and there. Think
about it.
Click to expand...

My school requires we pick either analog or digital circuit design as a mandatory elective. I took both, because I like a low GPA, yet my analog knowledge is crap compared to digital. What benefits would a PNP give over NPN for analog design? And if this sounds like a newb question that a graduating student should never ask, let me confess that my analog design labs have literally NEVER incorporated a PNP into any of our circuits.

Sorry for the tangent, tl;dr what benefits would a PNP add?
 

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