Several points you may try out.
You seem to have a headroom issue. Though biased with a 105u current, the total current from the input pair never reaches that value. Are you sure your process is targeted for 3.3V operation? The best way to check is to short the inputs to 1.65V, run a dc analysis and check the operating regions of all transistors, in particular M7, M1, M2 and M4.
Since you loaded out2 with a cap, why not do the same to out1?
And instead of fixing V23 at 1.65V, configure V23 to output 1.65-x and V24 to output 1.65+x. This will ensure that the common mode stays at 1.65V.
Any idea what is the threshold voltage for your process?