Dielectric loss in standard CMOS process

[vlsi_design2]

Hi,
1) I checked the metal stack of a few commercial CMOS node. The loss tangent of the dielectric is not defined. Is it because the dielectric losses are minimal compared to substrate and conductor losses in typical CMOS process?
2) Further, if the node provides an option of high res substrate layer below inductors, how do I include its effect in EM sim? Do I need to update the resistivity of substrate in the metal stack file?
Thanks!!

 

[D.A.(Tony)Stewart]

1)Yes.
Io^2*RdsOn*f (dynamic) is far greater than Vdd^2/Rleak *n (#FETs) static Pd loss unless f=0

2) I recall C depends on the conductor area/gap ratio times Dk times a constant.

So on Saturn PCB tools for PCBks you can enter the dimensions for h, w, l and Dk and compute C
As I recall a 10 thou trace over std thickness is about 3 " per pF then E field strength is Vdd/length in V/m as a point source then 1/r^2 rules apply for far field and linear loss for crosstalk parallel to the trace (near field). Ground perimeter may eliminate coupling crosstalk but raise C.

 

[dick_freebird]

Mainstream gate oxides are "close enough" to SiO2 for dielectric loss lookup.

The poly gate resistance ("access resistance") is likely to dominate an intrinsic FET turned on hard. FETs operated near threshold also have a messy-to-figure channel-as-bottom-plate series R and a secondary junction capacitance below.

Polar oxides like Si3N4 may contribute weirdness (hysteresis?) and I've seen mention of some nitriding of "mostly oxide" gates and I know nothing much about high-K or low-K dielectrics, though have seen that some treatment of HfO2 gives a memory element (so likely some kind of loss and linearity salad).

 

[volker@muehlhaus]

2) Further, if the node provides an option of high res substrate layer below inductors, how do I include its effect in EM sim? Do I need to update the resistivity of substrate in the metal stack file?

Yes, exactly.

 

[D.A.(Tony)Stewart]

2) Further, if the node provides an option of high res substrate layer below inductors, how do I include its effect in EM sim? Do I need to update the resistivity of substrate in the metal stack file?

When do you expect substrate leakage to ever affect EM sim with a low DCR inductor, except for capacitance?

 

[volker@muehlhaus]

@D.A.(Tony)Stewart In my RFIC EM simulations, inductor Q really depends on substrate conductivity, and high res substrate gives higher Q factor.

In MoM tools like ADS Momentum, we can't use local dielectric blocks, so this is simulated by creating another EM stackup with modified substrate conductivity.

 

[D.A.(Tony)Stewart]

@D.A.(Tony)Stewart In my RFIC EM simulations, inductor Q really depends on substrate conductivity, and high res substrate gives higher Q factor.

Are you talking about any Rp < 1Meg? where < 0.002pF matches at 100 MHz. I still don't see any significant effects of Rp in RFIC inductors.

 

[volker@muehlhaus]

at 100 MHz. I still don't see any significant effects of Rp in RFIC inductors.

I was assuming the question refers to real RF, i.e. millimeter wave CMOS design

 

[D.A.(Tony)Stewart]

I was assuming the question refers to real RF, i.e. millimeter wave CMOS design

Then what Rp and Cp do you suggest is "real"

 

[volker@muehlhaus]

Then what Rp and Cp do you suggest is "real"

The substrate loss is reflected by the shunt path elements of the Pi model. To get an idea about inductor microwave models, have a look here: https://muehlhaus.com/products/equivalent-circuit-model-fit-for-rfic-inductors

I don't want to argue with you, I just posted what I found when working on RFIC inductors at mm-wave frequencies, and how to simulate them. Maybe that applies to @vlsi_design2 work, or maybe not.

Have a great day!

 

[D.A.(Tony)Stewart]

Not playing Pickleball today which would make it better.... if I could.

But I would expect drive transistor Ro to be a thousand times more significant (lower) than inductor leakage.

I read once that Razavi recommends low-loss substrates for antennae but then declines to include it in any computations at 60GHz.
Other Q's were only 15 from drivers.

http://www.seas.ucla.edu/brweb/papers/Journals/BRTransI09.pdf

This is not an argument. I just like to support my assertions with a reference.

p.s. I can read the fF and nH but not the Q or f or Rp.

So are RFIC inductor series lossy (Rs) or parallel (Rp)?
value = Rsub (?) = ?