Dielectric loss in standard CMOS process

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Hi,
1) I checked the metal stack of a few commercial CMOS node. The loss tangent of the dielectric is not defined. Is it because the dielectric losses are minimal compared to substrate and conductor losses in typical CMOS process?
2) Further, if the node provides an option of high res substrate layer below inductors, how do I include its effect in EM sim? Do I need to update the resistivity of substrate in the metal stack file?
Thanks!!
 

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1)Yes.
Io^2*RdsOn*f (dynamic) is far greater than Vdd^2/Rleak *n (#FETs) static Pd loss unless f=0

2) I recall C depends on the conductor area/gap ratio times Dk times a constant.

So on Saturn PCB tools for PCBks you can enter the dimensions for h, w, l and Dk and compute C
As I recall a 10 thou trace over std thickness is about 3 " per pF then E field strength is Vdd/length in V/m as a point source then 1/r^2 rules apply for far field and linear loss for crosstalk parallel to the trace (near field). Ground perimeter may eliminate coupling crosstalk but raise C.
 

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Mainstream gate oxides are "close enough" to SiO2 for dielectric loss lookup.

The poly gate resistance ("access resistance") is likely to dominate an intrinsic FET turned on hard. FETs operated near threshold also have a messy-to-figure channel-as-bottom-plate series R and a secondary junction capacitance below.

Polar oxides like Si3N4 may contribute weirdness (hysteresis?) and I've seen mention of some nitriding of "mostly oxide" gates and I know nothing much about high-K or low-K dielectrics, though have seen that some treatment of HfO2 gives a memory element (so likely some kind of loss and linearity salad).
 

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