Did i get malfunctioning MCP3421

[barry]

the pullups have nothing to do with the alignment of the clock and data edges, that's under your program control.

 

[yefj]

Hello Barry, so by the updated photos in high accuracy and code i posted shown bellow (reply 18),you say that its not the pullup ressistor but the code.I have put the code also in reply 18.
I Have used the same code on the SI7021 sensor and it worked like a charm,i just changed the address and size of recieve buffer.

https://www.edaboard.com/threads/did-i-get-malfunctioning-mcp3421.396317/#post-1703177

 

[yefj]

Hello Barry ,i had the same "problem" in my working si7021 as shown bellow.And i got data perfectly back then
So i think its not a problem.
Can i conclude that the device i just not functioning?
Thanks.

 

[betwixt]

The pull-ups just change the rise time of the waveform. The rapid falling edge is caused by the I2C devices actively pulling it down but the rise time is limited by the current through the resistors charging the capacitance of the bus. That's why lower value resistors give a faster rise time. It isn't the rise or fall that is causing the problem and I suspect other I2C devices will be borderline too, its the delay between the SDA and SCL that causes the problem.

Except for the start and stop conditions, SDA is not allowed to change state while SCL is high and ideally it should be in the middle of the SCL low period. Your traces show both change simultaneously or very close to each other. You need to delay the whole SDA signal, not a change its rise time.

Brian.

 

[yefj]

Hello Brian,You saw my accurate photos on reply 18.
So the rise time is too high and i will try to connect 100 ohms in paralel to the 4.7Kohms on the PCB,Is that ok?
How do i create a delay between the SDA and SCL?
Thanks.

 

[barry]

SDA is not allowed to change state while SCL is high and ideally it should be in the middle of the SCL low period. Your traces show both change simultaneously or very close to each other. You need to delay the whole SDA signal, not a change its rise time.

Brian.

This is about the fourth time someone has said this. Are you paying attention, yefj???

 

[FvM]

The required SDA hold time after falling SCL edge according to I2C spec is 0, in so far the shown waveform isn't necessarily violating the spec.

--- Updated Jan 4, 2021 ---

It's nevertheless unusual that an I2C master stretches the timing spec to the limits. It might cause problems if the slave device isn't exactly compliant.

 

[yefj]

Hello FVM, So by the UPDATED data i showed in the link bellow and by the Working SI7021 photo You say its just the Way my EFR32FG14 works in general and no all devices can handle that.
So the problem is not with the MCP3421 but with the I2C periphery which make the SDA RISE just as CLK falls.

So if you agree the only choise i have left with, is try andconnect theMCP3421 with another microcontroller to conclude that the proble is with EFR32FG14 starter kit,

https://www.edaboard.com/threads/did-i-get-malfunctioning-mcp3421.396317/#post-1703177

 

[00kam]

Hello FVM, So by the UPDATED data i showed in the link bellow and by the Working SI7021 photo You say its just the Way my EFR32FG14 works in general and no all devices can handle that.
So the problem is not with the MCP3421 but with the I2C periphery which make the SDA RISE just as CLK falls.

So if you agree the only choise i have left with, is try andconnect theMCP3421 with another microcontroller to conclude that the proble is with EFR32FG14 starter kit,

https://www.edaboard.com/threads/did-i-get-malfunctioning-mcp3421.396317/#post-1703177

View attachment 166800

O.k try to connect MCP4321 with a micro- controller and choose " PIC16fxx or Atmega xx " because i guess many people her have handled interfaced with those micro- controllers before with many types of I2C and there is a good chance to fix were is the problem . please post a close and clear photo for the number of MCP4321 to ensure the right slave address of it before we start any thing

kamal