Plzhelp
Junior Member level 3
Hi guys,
Just for clarification.
1. STA has to be done on everything including the scan chains, otherwise there is no way you can close the path between the flops for timing. What I am trying to say is, when you are in SCAN_MODE, the path is from Q to SI of all flops in the chain. This path was never closed on timing because originally the path is from Q to combo logic to D of the next flop. Since you are using slow clock for scan, you can guarantee that no setup violation will occur but there is no guarantee for hold in the scan path. Hence you need to do STA for scan circuitry as well.
2. STA can be done to guarantee that your chip is working fine. But there are certain problems. Nowadays, chip sizes are huge, hence doing STA on everything is very difficult. Since STA is more manual in terms of figuring out the critical paths and analyze all other paths, it gets very hectic to guarantee that chip will be fault free only by doing STA. More over simulation is a much better option than STA because of the Static and Dynamic difference between the two.
3. Functional vectors can be used but it is not a feasible way. Imagine a design with 25 inputs and 1 output. The number of functional patterns you will need to verify this is 2^25. But if you consider single stuck at fault model and generate scan patterns for the same design, the maximum number of patterns you will need will be 2*25 which is way less than 2^25. Then, using the concept of fault equivalence and fault dominance, the patterns will further reduce down from 2*25 and still guaranting the perfection of testing.
4. We do both, timing and no timing simulations. Timing simulation is for the actual scenario, the way chip hardware will work. No timing simulation is more for debug. It is always easy to no timing simulations first because the simulation time decreases and whatever small issues and Mismatches you will get can be easily fixed through your no timing simulation. After running no timing simualtion and fixing all the bugs and Mismatches, if you run timing simulation and still get Mismatches then you can be sure that it is majorly a timing related issue (point the fingers at the SDF file majorly or some screw up) rather than your setup related issue because if it was setup related issue you would have got the same issue in your no timing simulation and would have fixed it right there.
I would also like to get a little more clarification from Maulin Sheth about his last answer. Was not able to understand the need of functional vector generation in DFT and how it helps in increasing the patterns.
Thanks and Regards.
Just for clarification.
1. STA has to be done on everything including the scan chains, otherwise there is no way you can close the path between the flops for timing. What I am trying to say is, when you are in SCAN_MODE, the path is from Q to SI of all flops in the chain. This path was never closed on timing because originally the path is from Q to combo logic to D of the next flop. Since you are using slow clock for scan, you can guarantee that no setup violation will occur but there is no guarantee for hold in the scan path. Hence you need to do STA for scan circuitry as well.
2. STA can be done to guarantee that your chip is working fine. But there are certain problems. Nowadays, chip sizes are huge, hence doing STA on everything is very difficult. Since STA is more manual in terms of figuring out the critical paths and analyze all other paths, it gets very hectic to guarantee that chip will be fault free only by doing STA. More over simulation is a much better option than STA because of the Static and Dynamic difference between the two.
3. Functional vectors can be used but it is not a feasible way. Imagine a design with 25 inputs and 1 output. The number of functional patterns you will need to verify this is 2^25. But if you consider single stuck at fault model and generate scan patterns for the same design, the maximum number of patterns you will need will be 2*25 which is way less than 2^25. Then, using the concept of fault equivalence and fault dominance, the patterns will further reduce down from 2*25 and still guaranting the perfection of testing.
4. We do both, timing and no timing simulations. Timing simulation is for the actual scenario, the way chip hardware will work. No timing simulation is more for debug. It is always easy to no timing simulations first because the simulation time decreases and whatever small issues and Mismatches you will get can be easily fixed through your no timing simulation. After running no timing simualtion and fixing all the bugs and Mismatches, if you run timing simulation and still get Mismatches then you can be sure that it is majorly a timing related issue (point the fingers at the SDF file majorly or some screw up) rather than your setup related issue because if it was setup related issue you would have got the same issue in your no timing simulation and would have fixed it right there.
I would also like to get a little more clarification from Maulin Sheth about his last answer. Was not able to understand the need of functional vector generation in DFT and how it helps in increasing the patterns.
Thanks and Regards.
