design transistor size in cmos process

Status
Not open for further replies.
S

saber67

Newbie level 1
Joined
Apr 25, 2014
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Visit site
Activity points
6
hi
please help me to design calculation of transistor size in cmos process

thanks
 

Hi saber67,

That’s a very open ended question. But I’d say as a starting point you can decide what current you want passing through the transistor and what overdive voltage is required (Vgs – Vt) --- where Vgs is the gate-source voltage and Vt is the threshold voltage.

Use the equation

IDS = K’(W/L)*(Vgs – Vt)^2

Where K’ is process parameters.

I suppose Im showing the formula here in the hope you will find this online for a better explanation 

https://books.google.ie/books?id=97...=onepage&q=IDS = K’(W/L)*(Vgs – Vt)^2&f=false
 

Start with the desired outcome(s) and work backward in
simulation or calculation. You don't have a desired outcome.
So any direction is as good as another.
 

Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…