design the block

[fragnen]

Data is coming with width 44 bits with a valid signal to a block as input. The block needs to send this incoming data as output of this block with data width of 60 bits and with a output valid signal for the output data. Can you please design this?

 

[D.A.(Tony)Stewart]

width= parallel
length = serial

Define your task with a timing and state diagram 1st before doing any design

 

[FvM]

module data_convert
(
  input   clk, reset,
  input   dv_i,
  input [43:0] x,
  output reg dv_o,
  output reg [59:0] y
);

reg [3:0]state;
reg [43:0] x_v1;
reg [43:0] x_v2;

always @ (posedge clk or posedge reset) begin
  if (reset)
    state <= 4'd0;
  else
    if (dv_i)
    begin
      x_v2 <= x_v1;
      x_v1 <= x;
      state <= state + 1'd1;
      dv_o <= 1;
      case (state)
        0:
          dv_o <= 0;
        1:
          y <= {x_v1, x[43:28]}; // 44 + 16
        2:
          y <= {x_v1[27:0], x[43:12]}; // 28 + 32
        3:
          dv_o <= 0;
        4:
          y <= {x_v2[11:0], x_v1, x[43:40]}; // 12 + 44 + 4
        5:
          y <= {x_v1[39:0], x[43:24]}; // 40 + 20
        6:
          y <= {x_v1[23:0], x[43:8]}; // 24 + 36
        7:
          dv_o <= 0;
        8:
          y <= {x_v2[7:0], x_v1, x[43:36]}; // 8 + 44 + 8
        9:
          y <= {x_v1[35:0], x[43:20]}; // 36 + 24
        10:
          y <= {x_v1[19:0], x[43:4]}; // 20 + 40
        11:
          dv_o <= 0;
        12:
          y <= {x_v2[3:0], x_v1, x[43:32]}; // 4 + 44 + 12
        13:
          y <= {x_v1[31:0], x[43:16]}; // 32 + 28
        14:
        begin
          y <= {x_v1[15:0], x}; // 16 + 44
          state <= 0;
        end
      endcase
    end
    else
      dv_o <= 0;
end
endmodule