design the block

[fragnen]

Data is coming with width 44 bits with a valid signal to a block as input. The block needs to send this incoming data as output of this block with data width of 60 bits and with a output valid signal for the output data. Can you please design this?

 

[barry]

Data is coming with width 44 bits with a valid signal to a block as input. The block needs to send this incoming data as output of this block with data width of 60 bits and with a output valid signal for the output data. Can you please design this?

Why do I get the sense that you are posting your homework questions here?

And, no, I won't design this for you. I am a professional, I get paid for what I do. I will gladly offer help and guidance, but I'm not going to do your work for you.

 

[D.A.(Tony)Stewart]

Data is coming with width 44 bits with a valid signal to a block as input. The block needs to send this incoming data as output of this block with data width of 60 bits and with a output valid signal for the output data. Can you please design this?

Sure if you forward your first born and year's salary

 

[FvM]

I presume you want to ask about design of a simple streaming interface (only valid signal no further handshake). But the specification is incomplete, we can't say if the design is trivial or involves critical points.

 

[fragnen]

FvM

That is the specification. To describe that pictorially , following is the picture

---

 

[FvM]

That's only a visualization of post #1, clock(s) missing. You may want to sketch a timing diagram.

 

[fragnen]

Sorry, this is a single clock design and write and read clock is same. Also there is only one reset to the system. If you think two resets will help, then two resets can be thought to be added.

 

[FvM]

The datapath of a clocked design has 1 to N clock cycles latency, the data valid signal has to be delayed by the same number of clock cycles.

 

[fragnen]

Sorry another matter needs to be mentioned.
After first 44 bits enters the block, then in next clock next 44 bits data enters the block. The block will take the first 44 bits and 16 bits from the next 44 bits to make the total transfer of 60 bits and that 60 bits will come out as the first output of the block with a valid signal. Then, the remaining 44-16=28 bits of the second input of 44 bits are added with 32 bits of the third input data of 44 bits and send as the second output of the block with a valid signal. In this way the input data ins transferred to the output.
Please state if there is any more query.

--- Updated Sep 18, 2021 ---

The datapath of a clocked design has 1 to N clock cycles latency, the data valid signal has to be delayed by the same number of clock cycles.

The input data can come to the block in every clock cycle as continuous valid data of 44 bits each.

 

[FvM]

Then, the remaining 44-16=28 bits of the second input of 44 bits are added with 32 bits of the third input data of 44 bits and send as the second output of the block with a valid signal.

Presume you mean "combined" rather than "added" here.

It's essentially a reasssembly of data bits. You'll get 11 output packets for 15 input packets. The output datavalid rate will be respectively 11/15 of the input rate.

--- Updated Sep 18, 2021 ---

There are different ways to set up the design. You can e.g. make a FSM with 15 states advanced cyclically, each representing y( n) as a specific combination of x( n), x(n-1) and x(n-2), including 4 states that generate no new output.

 

[fragnen]

The datapath of a clocked design has 1 to N clock cycles latency, the data valid signal has to be delayed by the same number of clock cycles.

The input data can come to the block in every clock cycle as continuous valid data of 44 bits each.

 

[FvM]

Why are you repeating this point? It's clear so far and considered in my suggestion.

Guess you should start to sketch the design.

 

[fragnen]

Presume you mean "combined" rather than "added" here.

Yes

--- Updated Sep 18, 2021 ---

It's essentially a reasssembly of data bits. You'll get 11 output packets for 15 input packets. The output datavalid rate will be respectively 11/15 of the input rate.

How to decide that after 15 inputs packets same thing repeats? Are you following and Lowest common multiple (LCM) or highest common factor (HCF) approach?

 

[FvM]

Yes, 4 is highest common factor.

 

[fragnen]

There are different ways to set up the design. You can e.g. make a FSM with 15 states advanced , each representing y( n) as a specific combination of x( n), x(n-1) and x(n-2), including 4 states that generate no new output.

Do you want to mean that state for y(0), y(1), y(2), y(3) will not have any output and output start coming for states with outputs y(4) to y(14)?

--- Updated Sep 18, 2021 ---

Since data at the input can come continuously. How will you store the data inside the block?

 

[FvM]

No. y(0) has no output, y(1) and y(2) have, y(3) not. Try yourself.

 

[fragnen]

Since data at the input can come continuously. How will you store the data inside the block?

 

[FvM]

Need storage registers for x(n-1) and x(n-2), already mentioned in post #10.

 

[fragnen]

Need storage registers for x(n-1) and x(n-2), already mentioned in post #10.

Where in post#10 it is mentioned that we need storage registers for x(n-1) and x(n-2)?

 

[FvM]

Using previous data x(n-1) and x(n-2) in assignments implies storage registers.