Design op amp in standard CMOS with High Voltage Protectio

Status
Not open for further replies.
T

tia_design

Advanced Member level 4
Joined
Feb 22, 2005
Messages
113
Helped
4
Reputation
8
Reaction score
1
Trophy points
1,298
Visit site
Activity points
2,217
The CMOS process I am using has maximum 6V supply voltage, I'm going to design an op amp using this process plus high voltage protection circuit (18V). Can anyone give me some idea. Thanks a lot!
 

Re: How to design high Voltage op amp in standard CMOS proce

Using de overdrive rules u can design..
 

Re: How to design high Voltage op amp in standard CMOS proce

Check if the process has high voltage NMOS devices where the drain is made using a N-well. This is one way to obtain a high-voltage NMOS in any CMOS process. AMS C35 for example has this device in the design kit.
 

Re: Design op amp in standard CMOS with High Voltage Prote

Here's an intersting paper showing these kind of devices, and mismatch modeling also.
 

It is not good way to design such 18V circuit in a process without HV device.
 

Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…