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DEEP nWELL for negative voltages

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deep well process

DNW is used as a well for PMOS. It also serves as an isolation from onther type of devices. In a twin well process, the subsrate serves as the P well of NMOS.
Deep N-well is a special layer used to supress Substrate Noise coupling injected by Digital Logic in Mixed Signal environment.During the digital logic switches from high to low or viceversa it injects noise which will be propagated through the substrate.Since the sensitive Analog circuit will be on same substrate, the noise can degrade the performance of the analog circuit.For example this noise can be amplified by an op-amp and its output will vary.

Sensitive analog blocks are surrounded by Gurad Rings and Deep N-well to suppress this kind of noise.
Generally DeepNwell is used to isolate NMOS from the substrate of other NMOS.
For example suppose all the NMOS in a amplifier is kept in PWELL (common substrate ) and that is connectet to gnd. and there is other NMOS whose substrate is connected to other potential not to gnd. In that case you need to isolate that NMOS from other NMOS, otherwise substrate will get short. So to avoid this DeepNwell is used.

So, for that you have to put that particular NMOS in a DeepNwell Layer and that MOS should sorround with a NWELL guardring.
Here DeepNwell is act as a bottom side and the NWELL guardring is act as a sidewall to seperate that particular NMOS from common P-type substrate.

For Example:- Suppose there is a Pond full of water and you want to put some instrument in that pond but at the same time water should not touch to that instrument. So for that you will construct something like BOX (with five faces, top side should open) and kept that instrument inside that BOX and put that BOX in the water, so that water will not able to touch that instrument. Similarly the bottom layer of the BOX is act as DEEPNWELL and the side wall of that BOX act as NWELL guardring. Hence the Psubstrat of that particular NMOS get isolated with other NMOS.
Deep N Well Process is a foundray method to islolate NMOS or for that mater PMOS.
this is done to prevent/reduce noise generated from substrate spl. during switching etc.
its like u have a n-well(N-) on 2 sides and bottom part is dep n-well(N+).
now with p-substrate u can form NMOS.

This structure isolates p-substate of the MOS from others. Hence less noisy.
This method is also used in digital ckts. spl. for deep submicron technologies
 

    V

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    egx

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    siilviu

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Re: deep nwell

It use high energy ion implantation

Avoid heating of wafer
 

Re: deep n-well purpose

so if we want to connect a different potential than vdd and gnd we can connect it by putting a deep nwell and then taking the source and drain connections

Since you opened the thread I guess we owe you an answer for this one too but it is not really clear what you mean:
- connect a different potential to what?
- are you talking about NFETs only or PFETs as well?

Please elaborate
 

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