D flip-flop in frequency divider

[adpot]

the DDS has to operate at 6Ghz...... i tried designing flip flop but that does not operate at such high frequency.....

 

[srieda]

CML is certainly not neccessary, reasonable (<say sub 1024 division ration) freq. dividers can easily be built out of plain vanilla CMOS logic and standard master slave flops and work at 800MHz even in 0.18, not to mention 0.13.

CML might have advantages in the dividers if you are after extremely low jitter and your loop BW is is very low since it is a very low noise topology (almost no switching noise since it always sinks the same current, even during value changes, this makes it very high power though).

You made my day, eteral_nan.... I have been trying to convey this only... and at last i find some support... thank you.. []
CML is not required for the design that is being discussed. I dont think its a good bargain for power... CML involves lots of static power dissipation...

 

[ahmed tolba]

thanks all, I made my latch using TSPC and it already works at 2.4GHz .......
but I want to know -generally and in clear words- the best cases for using CML, TSPC and any other latches......when I should use this or that ???