Current mirror unpredictable behavior

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Sambhav_1

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Hi,
I build a nmos current mirror with 50uA current source. The(w/l ) ratio is 320nm/150nm. Now when i see the mirrored current ,the value of current is coming out to be 54.56uA . Can anyone explain why is this happening and how can i minimize this error.
 

If the Vds of the 2 devices are not the same the ratio of input/output currents won't be 1. This is totally normal and predictable, the channel-length modulation causes.
Next time if you have a circuit please post the schematic please at least, otherwise everybody will guess what is the reason and hard to say a good solution.
 



How can i make tgese currents same
 

2 things I can suggest:
a, use much longer devices to decrease effect of channel-length modulation for bottom devices
b, use cascode devices which can guarantee constant Vds for bottom devices.
You can find the details in the literature, for example: Behzad Razavi - Design of analog CMOS integrated circuits
 

I guess you are reporting simulation results without exemplar variations between transistors. In this case, it's most likely a result of channel length modulation (Vds2 > Vds1). Refer to improved current mirror topologies. e.g. Wilson.

B.t.w., the current mirror behavior is non-ideal, but well predictable.
 

Another possible root cause for the current mismatch is IR drop on the ground net (if the two devices are not located "identically" with respect to ground net R network and its ports) - so that their Vgs voltages are mismatched.
 

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