manchuk
Newbie level 5
I am new to Synopsys design compiler. Trying to synthesis a verilog code to create a case insensitive netlist.
The verilog code has some uppercase parameters like NAME, DATE etc . These parameters are synthesised into the gate names like top_NAME top_DATE . I would like to get all lower case netlist with names like top_name or top_date.
I am using the commands
define_name_rules LOWERCASEONLY -allow "a-z 0-9 _"
change_names -rules LOWERCASEONLY -verbose -hier
These commands dont change the upper case parameters in HDL to lower case names in netlist. I would like to know if DC command can change the uppercase RTL names into lower case netlist during synthesis ?
The verilog code has some uppercase parameters like NAME, DATE etc . These parameters are synthesised into the gate names like top_NAME top_DATE . I would like to get all lower case netlist with names like top_name or top_date.
I am using the commands
define_name_rules LOWERCASEONLY -allow "a-z 0-9 _"
change_names -rules LOWERCASEONLY -verbose -hier
These commands dont change the upper case parameters in HDL to lower case names in netlist. I would like to know if DC command can change the uppercase RTL names into lower case netlist during synthesis ?