CPU @ RTL Design - Verilog (with complete documentation)

[echo47]

simple processor + verilog project

Hi guoshaojun, if you are referring to the RAR files in the first message, then you can click the "Free Mirror" links to download the files without using any points.

 

[atena]

kcpsm3.v

Introduction To The Design of CPU using RTL Approach.
This CPU is a simple 8-bit processor with 8-bit address bus. The architecture is based on accumulator-based design. The instruction set is grouped into few categories which is shown as below:

1. Data manipulation
a. ADD X Add the value in memory to the accumulator.
b. SUB X Subtract the value in memory to the accumulator.
c. XOR X Exclusive-OR logic operation value in memory to the accumulator.
d. AND X Perform AND logic operation value in memory to the accumulator.
e. ADR Add between registers.

2. Data transfer
a. MVI Move the immediate data to the specified register.
b. MVD Move the specified memory data to the specified register.
c. MOV Move data between registers.
d. LDA X Load the memory data to the accumulator.
e. STA X Load the accumulator to the memory data.

3. Program control
a. BRN X Branch if the value in the accumulator is negative.
b. JMP X Jump to a specified address.

6. Shifting
a. SHR Shift one bit of the register to the right.
b. SHL Shift one bit of the register to the left.

5. Miscellaneous
a. HALT Stay no operation.
b. NOP No operation until next instruction.

The design is using the Λltera Quαrtus II 7.2

Not exactly mistake but i think you have forgoten some important point. Allow me to fulfill your datasheet as much as i can plz, firstly we should also mention about the Interupt, for example with the simple processor like 85 we can have non-maskable interupt like TRAP ( we can define in VHDL as the infinite loop without EXIT instruction ) and obviously the maskable interupt infinite loop with conditional exit instruction, the interupt priority also should be considered.
Secondly you havent mentioned about the flag register, so that we can have the conditional jump instruction. With flag register will be tie with Acc... etc..
The concept of making a CPU or MPU is simply the concept of user defined data types, with each every instruction we enter ( can be done by define : type instruction is ) it will automatically do one or a group of predefine procedures.
But anyway, your concept is correct and from it we can make a simple CPU.

However, i have a question that i havent satisfied with my own answer till now. We know that with a MPU ( micro processor ) we consider 2 types of instruction : 1st 1 byte instruction such like in 8085 we have MOV A,B and the schedule clock cycle for it is 4. And 2 Byte instruction like MVI A,#data with 7 clock cycle. My question is : Why with the ins MVI A,#data the scheduled clk cycle is not 8 as the multiple of 4 ? Because the required opcode for MVI and MOV are both 1 byte, as the ip data.
Can any SYNOPSYS Tools like Design Compiler or Prime Time solve this problem ? If yes somebody plz explain me in detail ? Thanks in advance.

 

[yahootew3000]

1 byte shift register verilog

yahootew3000
Hi, brother. I have a question when I simulate your code given to me. My tools is QII 5.0, and the RAM ipcore transfer result is not the same as your document mentioned. When read RAM, the Data of RAM may be appear at the next edge of the clock, there are some problem.
and I refer to the RAM Megafunction User Guide from @ltera Website. The actual working operation is as my simulate status, so how you get the document result?

Hi, i simulated the codes using QII 7.1. It doesn't cause any problem to me. The documentation included the codes for each module. I design the simple CPU through hierarchical technique. Maybe you can try to pick some modules and give a test, chek whether it is same like mine.

Added after 3 minutes:

Introduction To The Design of CPU using RTL Approach.
This CPU is a simple 8-bit processor with 8-bit address bus. The architecture is based on accumulator-based design. The instruction set is grouped into few categories which is shown as below:

1. Data manipulation
a. ADD X Add the value in memory to the accumulator.
b. SUB X Subtract the value in memory to the accumulator.
c. XOR X Exclusive-OR logic operation value in memory to the accumulator.
d. AND X Perform AND logic operation value in memory to the accumulator.
e. ADR Add between registers.

2. Data transfer
a. MVI Move the immediate data to the specified register.
b. MVD Move the specified memory data to the specified register.
c. MOV Move data between registers.
d. LDA X Load the memory data to the accumulator.
e. STA X Load the accumulator to the memory data.

3. Program control
a. BRN X Branch if the value in the accumulator is negative.
b. JMP X Jump to a specified address.

6. Shifting
a. SHR Shift one bit of the register to the right.
b. SHL Shift one bit of the register to the left.

5. Miscellaneous
a. HALT Stay no operation.
b. NOP No operation until next instruction.

The design is using the Λltera Quαrtus II 7.2

Not exactly mistake but i think you have forgoten some important point. Allow me to fulfill your datasheet as much as i can plz, firstly we should also mention about the Interupt, for example with the simple processor like 85 we can have non-maskable interupt like TRAP ( we can define in VHDL as the infinite loop without EXIT instruction ) and obviously the maskable interupt infinite loop with conditional exit instruction, the interupt priority also should be considered.
Secondly you havent mentioned about the flag register, so that we can have the conditional jump instruction. With flag register will be tie with Acc... etc..
The concept of making a CPU or MPU is simply the concept of user defined data types, with each every instruction we enter ( can be done by define : type instruction is ) it will automatically do one or a group of predefine procedures.
But anyway, your concept is correct and from it we can make a simple CPU.

However, i have a question that i havent satisfied with my own answer till now. We know that with a MPU ( micro processor ) we consider 2 types of instruction : 1st 1 byte instruction such like in 8085 we have MOV A,B and the schedule clock cycle for it is 4. And 2 Byte instruction like MVI A,#data with 7 clock cycle. My question is : Why with the ins MVI A,#data the scheduled clk cycle is not 8 as the multiple of 4 ? Because the required opcode for MVI and MOV are both 1 byte, as the ip data.
Can any SYNOPSYS Tools like Design Compiler or Prime Time solve this problem ? If yes somebody plz explain me in detail ? Thanks in advance.

Hi,
I guess my design is just an introduciton to CPU design, speficically for beginner. Not as complex as the 85. SO, it only have the most fundamental operation only. I can say that it has the simply ISA (Instruction Set Architechture). Anywhere, thank for your comment.

 

[ashok_rudra]

simple processor design using verilog

i not having enough points to download
please mail me:ashok_rudra@yahoo.com

 

[yahootew3000]

what is cpu rtl

please click on the free mirror to download, no points is needed

 

[raymar2k]

thank you very much. good references.

 

[mafan88]

thank you very much ,i can learn it !

 

[kalyan_verilog]

byte is not factor for clock cycles. wheather it is 8 0r 16 or 32 etc

 

[flymolo500]

Lattice distributes free MICO8 and MICO32 RISC cores with verilog source code...

Does it still hold true? I have searched Lattice website for Mico32 sources and i didn't found it. What they have is LatticeMico32 System which is integrated with their ispLever/Diamond software.

Does anyone have experience porting Mico32 to non-lattice parts?

Is LatticeMico32 System generating vhdl/verilog output, which is acceptable for other vendor synthesis tools?

 

[chancelier]

where is this free mirror link ? ::shy::

 

[thit]

hello
i dont understand about operation on processor 8bit, can you talk detail, example you can explain ADDR processor operation